Vishay Siliconix SIC401ACD-T1-GE3
- Part No.:
- SIC401ACD-T1-GE3
- Manufacturer:
- Vishay Siliconix
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 32-PowerVFQFN
- Datasheet:
-
SIC401ACD-T1-GE3.pdf
- Description:
- IC REG DL BUCK/LNR SYNC MLP55-32
- Quantity:
- Payment:

- Shipping:

Inventory:15,337
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Product details
Overview
SIC401ACD-T1-GE3 from Vishay Siliconix is a 15 A synchronous buck regulator with integrated power MOSFETs, bootstrap switch, and a programmable 200 mA LDO in a PowerPAK® MLP32-55G package. It delivers up to 93 % peak efficiency across 3 V–17 V input, supports 0.6 V–VIN×0.75 output, operates at 200 kHz–1 MHz, and targets point-of-load regulation in notebook and server power rails.
For engineers reviewing the SIC401ACD-T1-GE3 datasheet, SIC401ACD-T1-GE3 pinout, SIC401ACD-T1-GE3 application, or SIC401ACD-T1-GE3 equivalent, key selection criteria include its pseudo-fixed-frequency adaptive on-time control, independent enable for switcher/LDO, selectable ultra-sonic power-save mode (SiC401A), and integrated valley current limit with temperature compensation.
Technical Context
The SIC401ACD-T1-GE3 implements pseudo-fixed-frequency adaptive on-time control using output ripple as the PWM ramp signal, eliminating error amplifier and compensation components. Its one-shot timer generates on-time proportional to VOUT and inversely proportional to VIN, enabling fast transient response and predictable frequency behavior.
It integrates dual power paths: a 15 A synchronous buck stage with internal high-side/low-side MOSFETs and LX node, plus a 200 mA programmable LDO with bypass logic and switch-over between VLDO and VOUT. The LDO can supply VDD bias or drive external n-channel MOSFETs, with independent ENL control and 1.2 V dropout at 100 mA.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input voltage range | 3 V to 17 V - supports wide-input industrial and computing rails including 5 V, 12 V, and 15 V bus systems. |
| Output current | 15 A continuous - enables single-chip point-of-load conversion for CPU/GPU core rails without external MOSFETs. |
| Switching frequency | 200 kHz to 1 MHz - programmable via tON resistor; higher frequencies reduce inductor size but increase switching loss. |
| Peak efficiency | 93 % - achieved at mid-load with ceramic output capacitors, enabling compact all-ceramic designs. |
| LDO output | Programmable 200 mA - configurable via FBL resistor divider; supports 3 V–5.5 V bias or external gate drive. |
| Control method | Pseudo-fixed-frequency adaptive on-time - eliminates loop compensation, reduces component count, and improves load transient response. |
| Package | PowerPAK MLP32-55G (5 mm × 5 mm) - thermally enhanced QFN with exposed thermal pad and multiple PGND/LX pins for low-inductance layout. |
Pinout & Package
Package: PowerPAK® MLP32-55G - 5 mm × 5 mm, 32-pin, thermally optimized QFN with exposed thermal pad (PAD 1, PAD 2, PAD 3). Features multiple parallel LX and PGND terminals to minimize parasitic inductance and improve thermal dissipation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| FB (Pin 1) | Feedback input | Connects to resistor divider from VOUT to AGND; sets output voltage with ±1 % reference accuracy. |
| VOUT (Pin 2) | Voltage sense / LDO switchover input | Senses switcher output; used internally to compare against VLDO for automatic switchover when |VLDO − VOUT| < 130 mV. |
| VDD (Pin 3) | Bias supply input/output | Accepts external 3–5.5 V supply or outputs LDO-regulated voltage; powers internal circuitry and gate drivers. |
| AGND (Pins 4, 30, PAD 1) | Analog ground | Reference for FB, FBL, SS, ILIM; must be separated from PGND and connected to quiet analog ground plane. |
| FBL (Pin 5) | LDO feedback input | Connects to resistor divider from VDD to AGND; programs LDO output voltage independently of main regulator. |
| VIN (Pins 6, 9–11, PAD 2) | Main input supply | 3–17 V input to high-side MOSFET and bootstrap circuit; multiple pins reduce IR drop and improve current sharing. |
| SS (Pin 7) | Soft-start capacitor | Internal 3 μA current source charges external capacitor; controls VOUT ramp rate to prevent inrush current. |
| BST (Pin 8) | Bootstrap supply | Connects 100 nF+ capacitor to LX; generates floating gate drive voltage for high-side MOSFET. |
| LXBST (Pin 13) | LX boost connection | Direct tie to BST capacitor; enhances bootstrap charge retention during high-duty-cycle operation. |
| LX (Pins 23–25, PAD 3) | Switching node | Drives external inductor; multiple pins reduce trace inductance and EMI; connects to internal high/low-side MOSFETs. |
| PGND (Pins 15–22) | Power ground | High-current return path for MOSFETs and inductor; must be solid copper pour tied to thermal pad for thermal performance. |
| PGOOD (Pin 26) | Open-drain status indicator | Asserts high-impedance when VOUT is within ±10 % of target; requires external pull-up for logic-level signaling. |
| ILIM (Pin 27) | Current limit programming | Resistor from ILIM to LXS sets valley current limit threshold (12.75–17.25 A); includes temperature compensation. |
| LXS (Pin 28) | LX sense | Connects to ILIM resistor; provides accurate sensing of inductor current zero-crossing for valley detection. |
| EN/PSV (Pin 29) | Enable / power-save control | Logic high enables ultra-sonic power-save mode (SiC401A); float enables forced continuous conduction mode. |
| tON (Pin 31) | On-time programming | Resistor to AGND sets nominal on-time (999–1220 ns @ 12 V/5 V); determines operating frequency in adaptive on-time mode. |
| ENL (Pin 32) | LDO enable | Drive low to disable LDO; use resistor divider from VIN to ENL to program VIN UVLO threshold (2.4–2.95 V). |
Key Features
| Feature | Design Value |
|---|---|
| All-ceramic solution support | Eliminates electrolytic capacitors by leveraging adaptive on-time control and stable loop dynamics with low-ESR MLCCs. |
| Independent switcher/LDO enable | EN/PSV and ENL pins allow separate sequencing and fault isolation-e.g., keep LDO active while disabling buck stage. |
| Ultra-sonic power-save mode (SiC401A) | Operates below 20 kHz only during light loads, avoiding audible noise while maintaining regulation without burst-mode artifacts. |
| Temperature-compensated current limit | Valley current limit adjusts with junction temperature to maintain consistent overcurrent protection across -40 °C to +125 °C. |
| Programmable soft-start and soft-shutdown | SS pin controls startup ramp; soft-shutdown discharges VOUT through internal FET when EN/PSV is pulled low. |
| Integrated bootstrap switch | Reduces external component count by integrating the bootstrap diode/switch, improving reliability and reducing board space. |
Applications
| Notebook Core Voltage Regulation | Server Point-of-Load Supply |
|---|---|
Use Scenario: Regulating 1.0–1.5 V core voltage for Intel/AMD mobile CPUs under dynamic load from 0 A to 15 A. IC Role / Device Role / Timing Role: Primary synchronous buck converter with integrated MOSFETs and adaptive on-time control for fast transient response. Use Value: Delivers 93 % peak efficiency and sub-100 µs load-step recovery using only ceramic output capacitors-reducing BOM cost and footprint. | Use Scenario: Providing stable 3.3 V or 5 V auxiliary rail for FPGA I/O banks or memory interfaces in 1U servers. IC Role / Device Role / Timing Role: Standalone buck regulator with programmable frequency and independent LDO for biasing auxiliary circuits. Use Value: Enables single-chip solution with 15 A capability and 200 mA LDO, eliminating discrete bias supplies and simplifying layout. |
| Digital HDTV SoC Power | Networking ASIC Core Rail |
Use Scenario: Powering ARM-based SoC cores (e.g., Amlogic, Realtek) requiring 0.8–1.2 V at up to 12 A in compact TV mainboards. IC Role / Device Role / Timing Role: High-efficiency microBUCK® regulator with ultra-sonic power-save mode to eliminate audible coil whine during standby. Use Value: Maintains regulation down to 1 mA load with no acoustic noise-critical for consumer audio-visual environments. | Use Scenario: Delivering 0.85 V core voltage to multi-core networking ASICs (e.g., Broadcom BCM56xx) with rapid load transients up to 10 A/µs. IC Role / Device Role / Timing Role: Adaptive on-time buck controller with valley current limit and fast comparator-based loop for < 20 µs transient recovery. Use Value: Achieves ±15 mV output deviation under 0→11 A load step-preserving ASIC timing margins without oversized bulk capacitance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MP2451DT-LF-Z | 3 A max output, no integrated LDO, fixed 2.2 MHz frequency, smaller TSOT23-8 package | Targeted at low-power peripherals-not suitable for 15 A core rails | Select only for sub-3 A auxiliary rails where size and fixed frequency outweigh need for high current or bias integration. |
| TPS54560QDGQRQ1 | 5.5 A max, external MOSFETs required, adjustable frequency 100 kHz–2.5 MHz, automotive-grade (-40 °C to +125 °C) | Requires external high-side/low-side FETs and driver; suited for harsh-environment industrial use | Choose when AEC-Q100 qualification, extended temperature, or design flexibility with discrete FETs is mandatory. |
Compared with MP2451DT-LF-Z and TPS54560QDGQRQ1, the SIC401ACD-T1-GE3 uniquely integrates 15 A power stages and a 200 mA LDO in a single 5 mm × 5 mm package, enabling compact, high-current point-of-load designs without external FETs or bias ICs-ideal for space-constrained computing and consumer electronics.
Availability
SIC401ACD-T1-GE3 is available at Aetrix Electronics and suitable for notebook core voltage regulation, server point-of-load supplies, digital HDTV SoC power, and networking ASIC core rails requiring stable component supply, long-term lifecycle support, and qualified automotive-grade alternatives.
Supply support for SIC401ACD-T1-GE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global leader in discrete semiconductors and passive components, specializing in high-performance power management solutions with emphasis on efficiency, thermal robustness, and reliability.
The SiC401A product line delivers integrated microBUCK® regulators targeting high-current, space-constrained DC/DC conversion in computing, consumer, and communications infrastructure-designed to replace multi-component solutions with single-chip efficiency and simplified layout.
FAQ
What is the maximum continuous output current supported by the SIC401ACD-T1-GE3?
The SIC401ACD-T1-GE3 supports 15 A continuous output current under recommended operating conditions (TA ≤ +85 °C, proper PCB thermal design). This rating assumes adequate copper area, thermal vias to inner layers, and airflow. Derating applies above +85 °C ambient or with insufficient heatsinking-refer to RthJA = 50 °C/W and maximum PD = 3.4 W at 25 °C ambient.
Does the SIC401ACD-T1-GE3 require external MOSFETs for operation?
No, the SIC401ACD-T1-GE3 integrates both high-side and low-side power MOSFETs, bootstrap switch, and gate drivers. It operates as a complete synchronous buck regulator with only external components: input/output capacitors, inductor, feedback resistors, BST capacitor, and optional soft-start capacitor. No external FETs are needed for 15 A operation.
How does the ultra-sonic power-save mode in the SIC401ACD-T1-GE3 differ from standard pulse-skipping mode?
The SIC401ACD-T1-GE3's ultra-sonic power-save mode (enabled via EN/PSV = VDD) operates switching below 20 kHz only during light loads, eliminating audible coil whine while maintaining tight output regulation. Unlike standard pulse-skipping, it avoids large output voltage excursions and EMI spikes by preserving controlled low-frequency bursts with consistent timing-verified in SiC401A-specific test data.
Can the internal LDO in the SIC401ACD-T1-GE3 be disabled and bypassed?
Yes, the internal 200 mA LDO can be fully disabled by grounding ENL (Pin 32), and bypassed by supplying an external 3–5.5 V bias to VDD (Pin 3). When bypassed, the LDO output is disconnected, allowing external bias to power gate drivers and internal circuitry-improving overall system efficiency by eliminating LDO dropout loss.
What is the purpose of the LXS (Pin 28) and ILIM (Pin 27) pins on the SIC401ACD-T1-GE3?
LXS (Pin 28) and ILIM (Pin 27) form a precision valley current-sense pair: LXS connects directly to the source of the low-side MOSFET, and ILIM accepts a resistor to LXS that sets the current-limit threshold (12.75–17.25 A). This arrangement enables accurate, temperature-compensated overcurrent protection without requiring a sense resistor in the high-side path.
SIC401ACD-T1-GE3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- microBUCK®
- Package/Case:
- 32-PowerVFQFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Topology:
- Step-Down (Buck) Synchronous (1), Linear (LDO) (1)
- Number of Outputs:
- 2
- Frequency - Switching:
- 200kHz ~ 1MHz
- Voltage/Current - Output 1:
- 0.6V ~ 5.5V, 15A
- Voltage/Current - Output 2:
- Adj to 0.75V, 200mA
- Voltage/Current - Output 3:
- -
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- No
- Voltage - Supply:
- 3V ~ 17V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- PowerPAK® MLP55-32
SIC401ACD-T1-GE3 FAQ
1.How can I place an order for SIC401ACD-T1-GE3 through Aetrix?
Please submit a Request for Quotation (RFQ) for SIC401ACD-T1-GE3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SIC401ACD-T1-GE3 reliable?
The price and inventory of SIC401ACD-T1-GE3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SIC401ACD-T1-GE3 is usually 5 days.
3.What payment methods are accepted for SIC401ACD-T1-GE3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SIC401ACD-T1-GE3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SIC401ACD-T1-GE3?
SIC401ACD-T1-GE3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SIC401ACD-T1-GE3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SIC401ACD-T1-GE3?
For technical support, including SIC401ACD-T1-GE3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SIC401ACD-T1-GE3 requirements.
6.How does Aetrix verify that SIC401ACD-T1-GE3 is sourced from the original manufacturer or authorized distributors?
All SIC401ACD-T1-GE3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SIC401ACD-T1-GE3 meets industry standards.
7.What is the process for return or replacement of SIC401ACD-T1-GE3?
All SIC401ACD-T1-GE3 units undergo pre-shipment inspection (PSI). If there is an issue with SIC401ACD-T1-GE3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SIC401ACD-T1-GE3 part is unused and in its original packaging.
Return procedure for SIC401ACD-T1-GE3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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