My Inquiry
My Account
Vishay Siliconix SIC402ACD-T1-GE3
- Part No.:
- SIC402ACD-T1-GE3
- Manufacturer:
- Vishay Siliconix
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 32-PowerVFQFN
- Datasheet:
-
SIC402ACD-T1-GE3.pdf
- Description:
- IC REG DL BUCK/LNR SYNC MLP55-32
- Quantity:
- Payment:
- Shipping:
Inventory:13,016
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SIC402ACD-T1-GE3 from Vishay Siliconix is a 10 A synchronous buck regulator with integrated power MOSFETs, bootstrap switch, and a programmable 200 mA LDO in a PowerPAK® MLP32-55G package. It operates from 3 V to 28 V input, delivers 0.6 V to VIN × 0.75 output, supports up to 1 MHz switching, and achieves >95 % peak efficiency-used for point-of-load regulation in notebook and server CPU core supplies.
For engineers reviewing the SIC402ACD-T1-GE3 datasheet, SIC402ACD-T1-GE3 pinout, SIC402ACD-T1-GE3 application, or SIC402ACD-T1-GE3 equivalent, key selection criteria include its ultrasonic power-save mode (min. ~25 kHz), adaptive on-time control for fast transient response, independent EN/PSV and ENL logic inputs, and integrated LDO bypass capability for external gate drive or auxiliary loads.
Technical Context
The SIC402ACD-T1-GE3 implements pseudo-fixed-frequency adaptive on-time control using output ripple as the PWM ramp signal, eliminating error amplifier compensation and enabling sub-100 ns transient response. Its one-shot timer generates on-time proportional to VOUT and inversely proportional to VIN, with frequency set via external resistor on tON pin (200 kHz–1 MHz range).
It integrates dual regulation paths: a main buck converter with cycle-by-cycle current limit, soft-start/soft-shutdown, and PGOOD output; plus a programmable LDO (0.75 V accuracy) with switch-over logic between VDD and VOUT, selectable enable (ENL), and 65–200 mA current limit depending on startup state.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input voltage range | 3 V to 28 V - supports wide-input industrial and computing rails including 5 V, 12 V, and 19 V adapters. |
| Output current | 10 A continuous - sufficient for high-current CPU/GPU core domains without external current sharing. |
| Switching frequency | 200 kHz to 1 MHz - adjustable via tON pin resistor; enables optimization of size (high fSW) vs. efficiency (low fSW). |
| Peak efficiency | >95 % - achieved at mid-load with ceramic output capacitors, reducing thermal stress and system cooling requirements. |
| LDO output | Programmable 200 mA, ±0.75 % accuracy - supplies gate drive bias or external n-MOSFETs; bypassable for highest efficiency. |
| Control method | Pseudo-fixed-frequency adaptive on-time - eliminates loop compensation, reduces component count, and improves load-step response. |
| Protection features | Cycle-by-cycle current limit, UVLO (programmable via ENL), OVP, UVP, thermal shutdown (150 °C), and smart power-save fault recovery. |
Pinout & Package
Package: PowerPAK® MLP32-55G (5 mm × 5 mm, 32-pin, exposed thermal pad).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| FB | Feedback input | Connects to resistor divider from VOUT to AGND; regulates output by comparing to 600 mV internal reference. |
| VOUT | Switcher output sense | Senses buck output voltage; also serves as input to internal LDO/VOUT switch-over logic. |
| VDD | Bias supply input/output | Accepts external 3–5.5 V or outputs LDO-regulated bias; powers internal circuitry and gate drivers. |
| AGND | Analog ground | Reference for FB, FBL, SS, and other precision analog inputs; must be separated from PGND for noise immunity. |
| FBL | LDO feedback input | Connects to resistor divider from VDD to AGND; programs LDO output voltage (e.g., 3.3 V or 5 V). |
| VIN | Main input supply | Primary power path (pins 6, 9–11, PAD 2); connects to bulk input capacitor and handles full 10 A current. |
| SS | Soft-start timing | Capacitor-connected node; internal 3 μA current source ramps voltage to control output voltage rise time. |
| BST | Bootstrap supply | Connects ≥100 nF capacitor to LX; provides floating gate drive voltage for high-side MOSFET. |
| PGOOD | Power-good indicator | Open-drain output; requires external pull-up; asserts high when VOUT is within ±10 % / +20 % of regulation. |
| ILIM | Current limit programming | Resistor-to-LXS sets valley current limit threshold (e.g., 4460 Ω → 10 A typical at VDD = 5 V). |
| EN/PSV | Switcher enable/power-save | Tri-state logic: grounded = disable; floated = forced continuous mode; VDD = ultrasonic power-save (SiC402A only). |
| ENL | LDO enable | Logic-controlled input; grounded = LDO off; driven high = LDO active; also used to program VIN UVLO threshold. |
| tON | On-time programming | Resistor-to-AGND sets switching frequency; 133 kΩ yields ~300 kHz at VIN = 15 V, VOUT = 5 V. |
| LX | Switching node | High-frequency phase node (pins 13, 17–25, 24, PAD 1 & 3); connects to inductor and BST capacitor. |
| PGND | Power ground | High-current return path (pins 15–22); must be low-inductance connection to input/output capacitors. |
Key Features
| Feature | Design Value |
|---|---|
| Ultrasonic power-save mode | SiC402A-specific: forces minimum ~25 kHz switching at light load to avoid audible noise while maintaining regulation. |
| Independent LDO and buck enable | ENL controls LDO separately from EN/PSV; allows LDO to power gate drivers before buck startup or remain active during buck shutdown. |
| Smart power-save protection | Disables power-save and activates low-side discharge if FB rises >10 % above nominal-prevents OVP shutdown due to leakage currents. |
| Programmable VIN UVLO | UVLO threshold (2.4–2.95 V rising) set via resistor divider from VIN to ENL; enables custom brown-in/out behavior. |
| Temperature-compensated current limit | First-order thermal compensation maintains consistent overcurrent trip across -40 °C to +125 °C junction temperature. |
| All-ceramic solution support | No ESR requirement on output capacitor; compatible with low-ESR MLCCs, reducing board area and cost vs. polymer/aluminum electrolytics. |
Applications
| Server CPU Core Supply | Notebook GPU Voltage Regulator |
|---|---|
Use Scenario: Provides tightly regulated 0.8–1.3 V at up to 10 A to modern x86 CPU cores under dynamic load transients. IC Role / Device Role / Timing Role: Primary buck controller with adaptive on-time control; manages power delivery, sequencing, and fault response. Use Value: Fast transient response (<100 ns) minimizes required output capacitance; ultrasonic PSM avoids audible coil whine during idle states. |
Use Scenario: Powers discrete or integrated GPU in thin-and-light notebooks requiring compact, efficient 1.0–1.2 V regulation. IC Role / Device Role / Timing Role: Standalone microBUCK regulator with integrated LDO for gate driver bias and auxiliary rail generation. Use Value: Single-chip solution eliminates discrete LDO and gate driver components; PowerPAK MLP32-55G footprint saves PCB space. |
| Digital HDTV SoC Power | Networking ASIC Point-of-Load |
Use Scenario: Supplies 1.1 V or 1.2 V core voltage to broadcast-grade video processing SoCs with strict ripple and noise limits. IC Role / Device Role / Timing Role: High-efficiency buck regulator with PGOOD signaling for system-level power sequencing and health monitoring. Use Value: >95 % peak efficiency reduces thermal load in sealed enclosures; programmable soft-start prevents inrush current damage to downstream logic. |
Use Scenario: Delivers 3.3 V or 5 V to high-speed SerDes, PHYs, or packet processors in enterprise switches and routers. IC Role / Device Role / Timing Role: Programmable-frequency buck with independent LDO for auxiliary bias; supports hot-swap and redundancy schemes. Use Value: Selectable power-save mode extends system uptime in low-traffic periods; robust OVP/UVP protects sensitive communication ICs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MP2315DJ-LF-Z | Monolithic 12 A buck (3–18 V), fixed 500 kHz, no integrated LDO, no ultrasonic PSM. | Lacks programmable LDO and ultrasonic mode; simpler design but requires external bias for gate drivers. | Choose MP2315 for cost-sensitive, fixed-frequency applications where LDO integration is unnecessary. |
| TPS546B24RVFT | 6 A PMBus-enabled buck (4–18 V), digital control, 0.5 % reference, no integrated LDO. | Supports telemetry and dynamic voltage scaling via PMBus; higher precision but larger footprint and firmware dependency. | Choose TPS546B24 for systems requiring real-time telemetry, margining, or multi-rail coordination. |
Compared with MP2315DJ-LF-Z and TPS546B24RVFT, the SIC402ACD-T1-GE3 uniquely combines 10 A analog buck regulation, ultrasonic power-save, and a programmable 200 mA LDO in a single 5 mm × 5 mm package-enabling compact, self-contained point-of-load designs without external bias or digital infrastructure.
Availability
SIC402ACD-T1-GE3 is available at Aetrix Electronics and suitable for notebook, server, and networking applications requiring stable component supply, long-term production continuity, and automotive-qualified thermal performance.
Supply support for SIC402ACD-T1-GE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global leader in discrete semiconductors and passive components, specializing in high-reliability power management solutions for computing, industrial, and communications markets.
The SiC402A/B product line was designed specifically for high-density, high-efficiency point-of-load conversion in space-constrained computing platforms-emphasizing integration, thermal performance, and ease of use without sacrificing transient response or protection robustness.
FAQ
What is the function of the EN/PSV pin on the SIC402ACD-T1-GE3?
The EN/PSV pin on the SIC402ACD-T1-GE3 controls both enable and power-save mode selection. When grounded, the buck regulator disables completely. When floated, it operates in forced continuous mode. When pulled to VDD, it enables ultrasonic power-save mode-unique to the SiC402A variant-which maintains switching above ~25 kHz at light loads to prevent audible noise. This tri-state functionality is documented in the S20-0483 Rev. D datasheet section "Enable and Power-Save Inputs".
Does the SIC402ACD-T1-GE3 require an external bootstrap capacitor, and what value is recommended?
Yes, the SIC402ACD-T1-GE3 requires an external bootstrap capacitor connected between BST and LX pins. The datasheet specifies a minimum value of 100 nF, rated for ≥16 V, with low ESR and placed as close as possible to the IC. This capacitor supplies the floating gate drive voltage for the high-side MOSFET during each switching cycle. Using a smaller or poorly placed capacitor risks insufficient high-side drive and potential shoot-through or dropout events.
How is the output voltage programmed on the SIC402ACD-T1-GE3?
The output voltage of the SIC402ACD-T1-GE3 is programmed using a resistor divider from VOUT to AGND, connected to the FB pin. The internal 600 mV reference determines regulation: VOUT = 0.6 V × (1 + R1/R2), where R1 is the top resistor (VOUT side) and R2 is the bottom resistor (AGND side). The datasheet confirms this relationship in Figure 25 and notes that the controller regulates the valley of the output ripple-not the DC average-so layout and capacitor ESR impact final accuracy.
Can the internal LDO of the SIC402ACD-T1-GE3 be disabled, and how is it controlled?
Yes, the internal LDO of the SIC402ACD-T1-GE3 can be fully disabled using the ENL pin. Driving ENL to AGND disables the LDO, regardless of VIN or VDD status. The LDO may also be enabled via logic-high signal or configured for UVLO programming using a resistor divider between VIN, ENL, and AGND. Its output (VDD) is used to bias internal circuitry or external gate drivers, and it can be bypassed entirely with an external 3–5.5 V supply applied directly to VDD.
What protection features does the SIC402ACD-T1-GE3 include, and how are they implemented?
The SIC402ACD-T1-GE3 includes cycle-by-cycle current limiting (via ILIM pin), input UVLO (programmable via ENL), output overvoltage and undervoltage protection (±10 % / +20 % thresholds), thermal shutdown at 150 °C with 10 °C hysteresis, and smart power-save fault recovery. These protections are implemented with dedicated comparators and internal logic-no external components required. For example, OVP triggers a hard shutdown after 5 µs delay, while smart PSAVE actively discharges VOUT via the low-side FET if FB exceeds +10 % nominal.
SIC402ACD-T1-GE3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- microBUCK®
- Package/Case:
- 32-PowerVFQFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Topology:
- Step-Down (Buck) Synchronous (1), Linear (LDO) (1)
- Number of Outputs:
- 2
- Frequency - Switching:
- 200kHz ~ 1MHz
- Voltage/Current - Output 1:
- 0.6V ~ 5.5V, 10A
- Voltage/Current - Output 2:
- Adj to 0.75V, 200mA
- Voltage/Current - Output 3:
- -
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- No
- Voltage - Supply:
- 3V ~ 28V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- PowerPAK® MLP55-32
SIC402ACD-T1-GE3 FAQ
1.How can I place an order for SIC402ACD-T1-GE3 through Aetrix?
Please submit a Request for Quotation (RFQ) for SIC402ACD-T1-GE3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SIC402ACD-T1-GE3 reliable?
The price and inventory of SIC402ACD-T1-GE3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SIC402ACD-T1-GE3 is usually 5 days.
3.What payment methods are accepted for SIC402ACD-T1-GE3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SIC402ACD-T1-GE3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SIC402ACD-T1-GE3?
SIC402ACD-T1-GE3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SIC402ACD-T1-GE3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SIC402ACD-T1-GE3?
For technical support, including SIC402ACD-T1-GE3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SIC402ACD-T1-GE3 requirements.
6.How does Aetrix verify that SIC402ACD-T1-GE3 is sourced from the original manufacturer or authorized distributors?
All SIC402ACD-T1-GE3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SIC402ACD-T1-GE3 meets industry standards.
7.What is the process for return or replacement of SIC402ACD-T1-GE3?
All SIC402ACD-T1-GE3 units undergo pre-shipment inspection (PSI). If there is an issue with SIC402ACD-T1-GE3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SIC402ACD-T1-GE3 part is unused and in its original packaging.
Return procedure for SIC402ACD-T1-GE3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SIC402ACD-T1-GE3 Tags
-
TPS6521905RHBR
Texas Instruments
-
MIC3385YHL-TR
Microchip Technology
-
A4402ELPTR-T
Allegro MicroSystems
-
LM26480SQ-AA/NOPB
Texas Instruments
-
A4402KLPTR-T
Allegro MicroSystems
-
BD71847AMWV-E2
ROHM Semiconductor
-
ADP5040ACPZ-1-R7
Analog Devices Inc.
-
LT3048IDC#TRPBF
Analog Devices Inc.
-
ADP5037ACPZ-R7
Analog Devices Inc.
-
XRP7714ILB-F
MaxLinear, Inc.
-
LTC3260EDE#TRPBF
Analog Devices Inc.
-
LTC3260EMSE#PBF
Analog Devices Inc.
Tech Hub
Comparator circuit design covering voltage thresholds, input limits, open-collector outputs, LM393 wiring, op-amp differences, hysteresis, timing, window detection and practical fault diagnosis.
Schmitt triggers use separate rising and falling thresholds to stabilize slow or noisy signals. This guide covers hysteresis, 74HC14 and 74HCT14 selection, comparator calculations, RC oscillators and p…
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
