Vishay Siliconix SIP21106DR-46-E3
- Part No.:
- SIP21106DR-46-E3
- Manufacturer:
- Vishay Siliconix
- Package:
- 5-TSSOP, SC-70-5, SOT-353
- Datasheet:
-
SIP21106DR-46-E3.pdf
- Description:
- IC REG LINEAR 4.6V 150MA SC70-5
- Quantity:
- Payment:

- Shipping:

Inventory:3,412
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SIP21106DR-46-E3 from Vishay Siliconix is a fixed-output 4.6 V, 150 mA low-noise low-dropout (LDO) regulator with 135 mV dropout at full load, 60 µV(rms) output noise (10 Hz–100 kHz), and ±1.0 % output voltage accuracy at 25 °C. It features ultra-low 35 µA ground current at 1 mA load, active output auto-discharge via 100 Ω NMOS during shutdown, and stable operation with 1 µF ceramic output capacitors - ideal for battery-powered RF subsystems in portable wireless handsets.
For engineers reviewing the SIP21106DR-46-E3 datasheet, SIP21106DR-46-E3 pinout, SIP21106DR-46-E3 application, or SIP21106DR-46-E3 equivalent, key selection criteria include its 4.6 V fixed output, SC70-5L package footprint (2.1 mm × 2.1 mm × 0.95 mm), BP pin for noise bypassing, EN-controlled shutdown, and compatibility with low-ESR ceramic capacitors without external compensation.
Technical Context
The SIP21106DR-46-E3 employs a P-channel MOSFET pass transistor (0.9 Ω typical RDS(on)) with a 1.2 V bandgap reference and error amplifier feedback loop to maintain regulation. Its architecture enables ultra-low quiescent current and eliminates base-drive losses inherent in PNP-based LDOs.
Startup includes an active pull-down circuit to improve transient response, while shutdown mode engages internal 100 Ω NMOS discharge and reduces supply current to ≤1 µA. The BP pin accepts a 10 nF capacitor to filter reference noise, directly enabling the specified 60 µV(rms) output noise performance across 1–150 mA load range.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 4.6 V ±1.0 % at 25 °C; ensures stable power rail for 4.5–4.7 V logic or analog circuits without external resistors. |
| Dropout Voltage | 135 mV at 150 mA load; allows operation down to VIN = 4.735 V while maintaining regulation - critical for single-cell Li-ion or dual-cell alkaline systems. |
| Output Noise | 60 µV(rms), 10 Hz–100 kHz bandwidth with 10 nF BP capacitor; meets stringent RF LNA and mixer supply noise requirements. |
| Ground Current | 35 µA typical at 1 mA load; extends battery life in standby mode for always-on sensor or communication modules. |
| Shutdown Current | ≤1 µA at 85 °C; enables deep-sleep power states in portable devices with minimal leakage impact. |
| Thermal Protection | 160 °C junction shutdown with 20 °C hysteresis; prevents permanent damage during sustained overload or poor PCB thermal design. |
| Auto-Discharge | 100 Ω internal NMOS discharge path; discharges 1 µF output cap to <100 mV in <1 ms after EN deactivation - avoids floating rails and latch-up risks. |
Pinout & Package
Package: SC70-5L (2.1 mm × 2.1 mm × 0.95 mm), RoHS-compliant, industrial temperature range (−40 °C to +85 °C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - EN | Enable control input | Active-high logic: ≥1.2 V enables regulation; ≤0.4 V disables output and activates auto-discharge; must not float. |
| 2 - GND | Power ground reference | Primary thermal and electrical return; requires direct connection to large PCB ground plane for thermal management and noise suppression. |
| 3 - VIN | Input supply | Accepts 2.2–6.0 V input; requires 1 µF ceramic bypass capacitor placed adjacent to pin to suppress line noise and support transient response. |
| 4 - VOUT | Regulated output | Delivers stable 4.6 V up to 150 mA; supports 1 µF ceramic output capacitor with ESR < 0.4 Ω for guaranteed stability across −40 °C to +85 °C. |
| 5 - BP | Noise bypass terminal | Connects to 10 nF ceramic capacitor to ground; filters internal reference noise and achieves 60 µV(rms) output noise specification. |
Key Features
| Feature | Design Value |
|---|---|
| Low-noise regulation | 60 µV(rms) output noise with 10 nF BP capacitor enables clean power for RF front-ends and precision analog circuits. |
| P-channel pass transistor | 0.9 Ω typical RDS(on) eliminates base-current loss, enabling 35 µA ground current at light load and extending battery runtime. |
| Fast transient response | Active pull-down circuit during startup improves output settling and load-step recovery - critical for burst-mode wireless transmission. |
| Integrated protection | 330 mA typical current limit and 160 °C thermal shutdown prevent damage under short-circuit or overtemperature conditions. |
| SC70-5L footprint | 2.1 mm × 2.1 mm area saves board space in compact portable designs while supporting manual rework and automated assembly. |
Applications
| Cellular Handset RF Subsystem | Portable Digital Camera Sensor Power |
|---|---|
Use Scenario: Powering LNA, mixer, and VCO stages in GSM/UMTS/WCDMA transceivers where supply noise directly impacts EVM and adjacent channel rejection. IC Role / Device Role / Timing Role: Primary 4.6 V low-noise bias rail regulator with BP-filtered reference ensuring spectral purity of RF signal chain. Use Value: 60 µV(rms) noise and 135 mV dropout enable >40 dB PSRR at 100 kHz, reducing phase noise and improving receiver sensitivity by up to 2 dB. | Use Scenario: Supplying CMOS image sensor analog core and ADC reference in sub-20 mm thick digital cameras. IC Role / Device Role / Timing Role: Fixed 4.6 V LDO delivering regulated power during high-current pixel readout bursts (100–150 mA peaks). Use Value: Active pull-down and 100 Ω auto-discharge ensure rapid rail collapse between frames, eliminating ghosting and enabling precise exposure timing control. |
| Wireless Modem Baseband Core | MP3 Player Audio DAC Supply |
Use Scenario: Providing clean 4.6 V supply to baseband processor I/O banks and memory interfaces in embedded LTE modems. IC Role / Device Role / Timing Role: Low-quiescent LDO decoupling noisy digital switching noise from sensitive analog peripherals. Use Value: 35 µA ground current at 1 mA load and 1 µA shutdown current extend battery life in always-connected IoT modem applications. | Use Scenario: Powering stereo audio DAC and headphone amplifier in portable MP3 players requiring ultra-low THD+N. IC Role / Device Role / Timing Role: Ultra-low-noise 4.6 V regulator feeding DAC reference and analog output stage. Use Value: 60 µV(rms) noise floor ensures <−105 dB THD+N performance, preserving dynamic range and minimizing audible hiss. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LDO regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MCP1700T-4602E/TT | 300 mA rated output, 170 mV dropout at 250 mA, 30 µA quiescent current, SOT-23-5 package | Larger dropout and higher max current; lacks BP pin for noise filtering - unsuitable for RF-sensitive designs | Select when higher output current is required and noise performance is secondary; verify thermal derating for SC70-5L footprint replacement. |
| TCS21106DVP-46-E3 | Same SiP21106 family, TSC75-6L package (1.6 mm × 1.6 mm), identical electrical specs, 6-pin layout with NC pin | Smaller footprint but different pin count and layout; requires PCB redesign; same noise and regulation performance | Choose for space-constrained designs where 1.6 mm × 1.6 mm size is mandatory and layout revision is acceptable. |
Compared with MCP1700T-4602E/TT and TCS21106DVP-46-E3, SIP21106DR-46-E3 uniquely delivers 60 µV(rms) noise with BP filtering in the smallest SC70-5L footprint, making it irreplaceable for RF and precision analog applications where spectral purity is non-negotiable.
Availability
SIP21106DR-46-E3 is available at Aetrix Electronics and suitable for cellular handsets, portable digital cameras, wireless modems, and MP3 players requiring stable component supply with known end-of-life status and legacy inventory support.
Supply support for SIP21106DR-46-E3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix designs high-performance discrete semiconductors and integrated power solutions, emphasizing reliability, efficiency, and miniaturization for demanding industrial and consumer applications.
The SiP21106 series was engineered specifically for ultra-low-noise, low-quiescent-power regulation in battery-operated portable electronics - prioritizing RF immunity, fast transient response, and minimal board area.
FAQ
What is the maximum input voltage rating for SIP21106DR-46-E3?
The absolute maximum input voltage for SIP21106DR-46-E3 is 6.5 V relative to GND. For reliable continuous operation, the recommended input range is 2.2 V to 6.0 V per the datasheet's Recommended Operating Range. Exceeding 6.5 V may cause permanent damage, and operation above 6.0 V voids guaranteed performance specifications including dropout, noise, and accuracy.
Does SIP21106DR-46-E3 require an external bypass capacitor on the BP pin?
Yes - SIP21106DR-46-E3 requires a 10 nF ceramic capacitor connected from the BP pin to GND to achieve its specified 60 µV(rms) output noise performance. Without this capacitor, output noise rises to 350 µV(rms). The BP pin is not functional for noise reduction beyond 50 nF, and larger values degrade startup time and increase quiescent current.
What is the purpose of the EN pin on SIP21106DR-46-E3, and what voltage levels enable/disable regulation?
The EN pin controls regulator activation: applying ≥1.2 V (typical) turns SIP21106DR-46-E3 on, while ≤0.4 V (typical) forces shutdown with auto-discharge. The EN pin draws only 9 nA typical current, enabling direct microcontroller GPIO control without level-shifting. Leaving EN floating is prohibited - it must be tied to VIN or actively driven.
Can SIP21106DR-46-E3 operate stably with a 1 µF ceramic output capacitor?
Yes - SIP21106DR-46-E3 is explicitly designed for stable operation with a minimum 1 µF ceramic output capacitor (6 nF/mA rule yields ~1 µF at 150 mA). Stability requires ESR < 0.4 Ω; X7R or Y7R dielectrics are recommended. Z5U/Y5V types may require ≥2.2 µF to maintain phase margin across −40 °C to +85 °C.
Is SIP21106DR-46-E3 still in production, and what is its lifecycle status?
SIP21106DR-46-E3 is End of Life per Vishay documentation (Document 74442, Rev. G), with Last Available Purchase Date of 31-Dec-2014. Aetrix Electronics maintains legacy inventory and provides traceable, tested stock for ongoing production support, including full datasheet compliance verification and application-specific validation guidance for SIP21106DR-46-E3 deployments.
SIP21106DR-46-E3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- -
- Package/Case:
- 5-TSSOP, SC-70-5, SOT-353
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 6V
- Voltage - Output (Min/Fixed):
- 4.6V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.22V @ 150mA
- Current - Output:
- 150mA
- Current - Quiescent (Iq):
- 85 µA
- Current - Supply (Max):
- -
- PSRR:
- 75dB ~ 40dB (1kHz ~ 100kHz)
- Control Features:
- Enable
- Protection Features:
- Over Temperature, Short Circuit
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SC-70-5
SIP21106DR-46-E3 FAQ
1.How can I place an order for SIP21106DR-46-E3 through Aetrix?
Please submit a Request for Quotation (RFQ) for SIP21106DR-46-E3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SIP21106DR-46-E3 reliable?
The price and inventory of SIP21106DR-46-E3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SIP21106DR-46-E3 is usually 5 days.
3.What payment methods are accepted for SIP21106DR-46-E3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SIP21106DR-46-E3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SIP21106DR-46-E3?
SIP21106DR-46-E3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SIP21106DR-46-E3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SIP21106DR-46-E3?
For technical support, including SIP21106DR-46-E3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SIP21106DR-46-E3 requirements.
6.How does Aetrix verify that SIP21106DR-46-E3 is sourced from the original manufacturer or authorized distributors?
All SIP21106DR-46-E3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SIP21106DR-46-E3 meets industry standards.
7.What is the process for return or replacement of SIP21106DR-46-E3?
All SIP21106DR-46-E3 units undergo pre-shipment inspection (PSI). If there is an issue with SIP21106DR-46-E3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SIP21106DR-46-E3 part is unused and in its original packaging.
Return procedure for SIP21106DR-46-E3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SIP21106DR-46-E3 Tags

-
MIC5504-1.8YM5-TR
Microchip Technology

-
MIC5504-3.3YM5-TR
Microchip Technology

-
MIC5365-3.0YC5-TR
Microchip Technology

-
MIC5365-1.8YC5-TR
Microchip Technology

-
MIC5365-2.5YC5-TR
Microchip Technology

-
MIC5365-3.3YC5-TR
Microchip Technology

-
MIC5365-3.3YD5-TR
Microchip Technology

-
MIC5317-3.3YM5-TR
Microchip Technology

-
TLV1117LV33DCYR
Texas Instruments

-
MIC5317-3.3YMT-TZ
Microchip Technology

-
MIC5528-3.3YMT-TR
Microchip Technology

-
TLV75801PDRVR
Texas Instruments
Tech Hub
Comparator circuit design covering voltage thresholds, input limits, open-collector outputs, LM393 wiring, op-amp differences, hysteresis, timing, window detection and practical fault diagnosis.
Schmitt triggers use separate rising and falling thresholds to stabilize slow or noisy signals. This guide covers hysteresis, 74HC14 and 74HCT14 selection, comparator calculations, RC oscillators and p…
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

