Vishay Siliconix SIP21106DVP-28-E3
- Part No.:
- SIP21106DVP-28-E3
- Manufacturer:
- Vishay Siliconix
- Package:
- PowerPAK® TSC-75-6
- Datasheet:
-
SIP21106DVP-28-E3.pdf
- Description:
- IC REG LIN 2.8V 150MA TSC75-6
- Quantity:
- Payment:

- Shipping:

Inventory:4,599
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Product details
Overview
SIP21106DVP-28-E3 from Vishay Siliconix is a fixed-output 2.8 V, 150 mA low-noise low-dropout (LDO) regulator with BiCMOS process technology, 135 mV dropout at full load, 60 µV(rms) output noise (10 Hz–100 kHz), and ultra-low 35 µA ground current at 1 mA - designed for battery-powered RF-sensitive applications such as cellular handsets and digital cameras.
For engineers reviewing the SIP21106DVP-28-E3 datasheet, SIP21106DVP-28-E3 pinout, SIP21106DVP-28-E3 application, or SIP21106DVP-28-E3 equivalent, key selection criteria include output voltage accuracy (±1.0 % at 25 °C), shutdown current (<1 µA), auto-discharge capability (100 Ω internal NMOS), thermal protection (160 °C trip), and compatibility with 1 µF ceramic output capacitors.
Technical Context
The SIP21106DVP-28-E3 employs a P-channel MOSFET pass transistor with typical 0.9 Ω on-resistance, enabling low quiescent current and eliminating base-drive losses inherent in PNP-based LDOs. Its error amplifier compares a stable 1.2 V bandgap reference against feedback from the fixed internal resistor divider to regulate output voltage.
Startup includes an active pull-down circuit improving transient response, while shutdown mode activates an internal 100 Ω NMOS discharge path to ground the output within <1 ms for a 1 µF capacitor. The BP pin accepts a 10 nF bypass capacitor to reduce output noise without compromising stability.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 2.8 V ±1.0 % at 25 °C; ensures stable core supply for 2.8 V logic rails without external resistors. |
| Dropout Voltage | 135 mV at 150 mA load; enables regulation down to VIN = 2.935 V, extending usable battery range in single-cell Li-ion systems. |
| Output Noise | 60 µV(rms), 10 Hz–100 kHz bandwidth with 10 nF BP capacitor; meets stringent RF section noise requirements in wireless handsets. |
| Ground Current | 35 µA typical at 1 mA load; minimizes standby power loss in always-on subsystems like real-time clocks or sensor interfaces. |
| Shutdown Current | ≤1 µA maximum at 85 °C; preserves battery charge during extended sleep modes in portable electronics. |
| Auto-Discharge | 100 Ω internal NMOS discharge path; safely drains output capacitance in <1 ms, preventing unintended wake-up or latch-up in sequenced power systems. |
| Thermal Protection | 160 °C junction shutdown with 20 °C hysteresis; prevents permanent damage during sustained overload or poor PCB thermal design. |
Pinout & Package
TSC75-6L package: 1.6 mm × 1.6 mm × 0.55 mm ultra-thin lead-free surface-mount package rated for -40 °C to +85 °C ambient operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (EN) | Enable input | Active-high control: ≥1.2 V enables regulation; ≤0.4 V disables output and activates auto-discharge. |
| 2 (GND) | Power ground | Primary thermal and electrical return path; must connect directly to large PCB ground plane for thermal management. |
| 3 (VIN) | Input supply | Accepts 2.2–6.0 V input; requires 1 µF ceramic bypass capacitor to ground for line-transient immunity. |
| 4 (VOUT) | Regulated output | Delivers stable 2.8 V up to 150 mA; supports 1 µF ceramic output capacitor for full-load stability. |
| 5 (NC) | No connection | Internally unconnected; must remain floating - no external tie or routing permitted. |
| 6 (BP) | Noise bypass | Connects to 10 nF ceramic capacitor to ground to filter high-frequency noise; critical for achieving 60 µV(rms) performance. |
Key Features
| Feature | Design Value |
|---|---|
| Low-noise architecture | 60 µV(rms) output noise with 10 nF BP capacitor enables direct powering of RF transceivers and ADC references. |
| P-channel pass transistor | 0.9 Ω typical RDS(on) eliminates base-current losses, enabling 35 µA ground current at light loads. |
| Integrated auto-discharge | 100 Ω internal NMOS discharges VOUT to ground in <1 ms upon EN deactivation, eliminating hold-up voltage issues. |
| Full-temperature accuracy | ±2.5 % output voltage tolerance over -40 °C to +85 °C ensures reliable operation across industrial environments. |
| Robust protection suite | 330 mA current limit (typical) and 160 °C thermal shutdown prevent damage during short-circuit or thermal overload events. |
Applications
| Cellular Handset Power Rail | Wireless Modem RF Section |
|---|---|
Use Scenario: Supplying 2.8 V bias to GSM/UMTS power amplifiers and front-end modules in compact handheld devices. IC Role / Device Role / Timing Role: Primary LDO delivering clean, regulated 2.8 V from shared battery rail with fast transient response to PA burst-mode current demands. Use Value: 135 mV dropout extends talk time by maintaining regulation until battery drops to 2.935 V; 60 µV(rms) noise prevents EVM degradation in transmit paths. | Use Scenario: Providing low-noise 2.8 V supply to RF synthesizers and mixer ICs in embedded LTE/Wi-Fi modems. IC Role / Device Role / Timing Role: Dedicated low-noise LDO isolating sensitive analog RF circuitry from noisy digital supply domains. Use Value: BP pin + 10 nF capacitor reduces broadband phase noise contribution; 1 µF ceramic compatibility simplifies layout in space-constrained modules. |
| Digital Camera Image Sensor Bias | MP3 Player Audio Codec Supply |
Use Scenario: Powering CMOS image sensor analog front-end and column ADC in battery-operated digital still/video cameras. IC Role / Device Role / Timing Role: Fixed 2.8 V LDO supplying precision analog bias where PSRR and noise directly impact SNR and dynamic range. Use Value: 75 dB PSRR at 1 kHz rejects switching noise from DC-DC converters; ±1.0 % room-temp accuracy ensures consistent sensor gain calibration. | Use Scenario: Delivering stable 2.8 V to stereo audio DACs and headphone amplifiers in portable music players. IC Role / Device Role / Timing Role: Low-quiescent LDO supporting playback-only operation with minimal battery drain during extended listening sessions. Use Value: 35 µA ground current at 1 mA load extends battery life; auto-discharge clears residual voltage before system reset, preventing pop/click artifacts. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LDO regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MCP1700T-2802E/TT | 300 mA output, 1.6 µA quiescent current, no BP pin or noise-bypass capability | Lacks low-noise optimization; unsuitable for RF or high-SNR analog circuits | Select only when ultra-low IQ dominates over noise performance and higher output current is required |
| TPS78228DRVR | 150 mA output, 500 nA shutdown current, 17 µV(rms) noise, but requires 2.2 µF minimum COUT | Superior noise and shutdown specs, but larger output capacitor increases BOM cost and board area | Prefer when lowest possible noise and shutdown current are mandatory, and 2.2 µF COUT is acceptable |
Compared with MCP1700T-2802E/TT and TPS78228DRVR, the SIP21106DVP-28-E3 uniquely balances 60 µV(rms) noise, 135 mV dropout, and 1 µF ceramic capacitor support - making it optimal for space-constrained, battery-powered RF systems where noise, efficiency, and component count are co-optimized.
Availability
SIP21106DVP-28-E3 is available at Aetrix Electronics and suitable for cellular handsets, digital cameras, and wireless modems requiring stable component supply despite end-of-life status.
Supply support for SIP21106DVP-28-E3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix designs and manufactures high-performance discrete semiconductors and integrated power solutions, emphasizing reliability, efficiency, and miniaturization for demanding electronic systems.
The SiP21106 family targets portable, battery-powered applications needing ultra-low noise, low dropout, and minimal quiescent current - particularly in RF, imaging, and audio subsystems where power integrity directly impacts signal fidelity.
FAQ
What is the maximum input voltage rating for the SIP21106DVP-28-E3?
The SIP21106DVP-28-E3 has an absolute maximum input voltage of 6.5 V relative to GND. Its recommended operating input range is 2.2 V to 6.0 V. Exceeding 6.5 V may cause permanent damage, and operation below 2.2 V prevents regulation due to dropout constraints. Always observe derating curves for thermal limits at elevated ambient temperatures.
Does the SIP21106DVP-28-E3 require an external bypass capacitor on the BP pin?
Yes - the SIP21106DVP-28-E3 requires a 10 nF ceramic capacitor between the BP pin and GND to achieve its specified 60 µV(rms) output noise performance. Omitting this capacitor increases noise to ~350 µV(rms). The device remains stable without it, but noise-sensitive applications like RF transceivers will not meet specification.
What is the function of the NC pin on the SIP21106DVP-28-E3 TSC75-6L package?
The NC (No Connection) pin on the SIP21106DVP-28-E3 TSC75-6L package is internally unconnected and must remain electrically floating. It is not tied to any internal node and serves no functional purpose. Do not route traces to or from this pin, and avoid soldering or grounding it, as doing so may compromise package integrity or thermal performance.
How does the SIP21106DVP-28-E3 behave during shutdown?
When the EN pin voltage falls below 0.4 V, the SIP21106DVP-28-E3 enters shutdown mode: output is disabled, ground current drops to ≤1 µA, and the internal 100 Ω NMOS discharge path connects VOUT to GND. This discharges a 1 µF output capacitor in under 1 ms, ensuring rapid, controlled power-down without residual voltage affecting downstream circuitry.
Can the SIP21106DVP-28-E3 be used with ceramic output capacitors smaller than 1 µF?
No - the SIP21106DVP-28-E3 requires a minimum 1 µF ceramic output capacitor for guaranteed stability across the full -40 °C to +85 °C temperature range and 1 mA to 150 mA load. Using smaller values risks oscillation or degraded transient response. The datasheet specifies stability with "6 nF/mA" - i.e., ≥0.9 µF at 150 mA - but recommends 1 µF as the robust design margin.
SIP21106DVP-28-E3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- -
- Package/Case:
- PowerPAK® TSC-75-6
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 6V
- Voltage - Output (Min/Fixed):
- 2.8V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.22V @ 150mA
- Current - Output:
- 150mA
- Current - Quiescent (Iq):
- 85 µA
- Current - Supply (Max):
- -
- PSRR:
- 75dB ~ 40dB (1kHz ~ 100kHz)
- Control Features:
- Enable
- Protection Features:
- Over Temperature, Short Circuit
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- PowerPAK® TSC75-6
SIP21106DVP-28-E3 FAQ
1.How can I place an order for SIP21106DVP-28-E3 through Aetrix?
Please submit a Request for Quotation (RFQ) for SIP21106DVP-28-E3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SIP21106DVP-28-E3 reliable?
The price and inventory of SIP21106DVP-28-E3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SIP21106DVP-28-E3 is usually 5 days.
3.What payment methods are accepted for SIP21106DVP-28-E3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SIP21106DVP-28-E3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SIP21106DVP-28-E3?
SIP21106DVP-28-E3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SIP21106DVP-28-E3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SIP21106DVP-28-E3?
For technical support, including SIP21106DVP-28-E3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SIP21106DVP-28-E3 requirements.
6.How does Aetrix verify that SIP21106DVP-28-E3 is sourced from the original manufacturer or authorized distributors?
All SIP21106DVP-28-E3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SIP21106DVP-28-E3 meets industry standards.
7.What is the process for return or replacement of SIP21106DVP-28-E3?
All SIP21106DVP-28-E3 units undergo pre-shipment inspection (PSI). If there is an issue with SIP21106DVP-28-E3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SIP21106DVP-28-E3 part is unused and in its original packaging.
Return procedure for SIP21106DVP-28-E3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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