Vishay Siliconix SIP21106DVP-46-E3
- Part No.:
- SIP21106DVP-46-E3
- Manufacturer:
- Vishay Siliconix
- Package:
- PowerPAK® TSC-75-6
- Datasheet:
-
SIP21106DVP-46-E3.pdf
- Description:
- IC REG LIN 4.6V 150MA TSC75-6
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SIP21106DVP-46-E3 from Vishay Siliconix is a fixed-output 4.6 V, 150 mA low-noise LDO voltage regulator in TSC75-6L package. It features 135 mV dropout at full load, 60 µV(rms) output noise (10 Hz–100 kHz), 1.0 % output accuracy at 25 °C, and ultra-low 35 µA ground current at 1 mA - optimized for battery-powered RF systems like cellular handsets and wireless modems.
For engineers reviewing the SIP21106DVP-46-E3 datasheet, SIP21106DVP-46-E3 pinout, SIP21106DVP-46-E3 application, or SIP21106DVP-46-E3 equivalent, key selection criteria include its low-noise BP pin architecture, auto-discharge capability during shutdown, industrial temperature range (−40 °C to +85 °C), and compatibility with 1 µF ceramic output capacitors without external compensation.
Technical Context
The SIP21106DVP-46-E3 uses a P-channel MOSFET pass transistor with 0.9 Ω typical on-resistance, enabling low dropout and near-zero gate drive current. Its bandgap reference (1.2 V) and error amplifier maintain regulation across input voltages from 2.2 V to 6 V and load currents up to 150 mA.
Startup includes active pull-down for fast transient response; shutdown mode enables 100 Ω NMOS auto-discharge of VOUT and reduces supply current to ≤1 µA at 85 °C. The BP pin accepts a 10 nF bypass capacitor to achieve 60 µV(rms) noise performance across full load range.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 4.6 V ±2.5 % over −40 °C to +85 °C - ensures stable core/sensor rail in portable electronics. |
| Dropout Voltage | 135 mV at 150 mA - enables operation down to VIN = 4.735 V, extending usable battery range in Li-ion systems. |
| Output Noise | 60 µV(rms), 10 Hz–100 kHz with 10 nF BP cap - meets stringent RF section noise requirements without additional filtering. |
| Ground Current | 35 µA (typ) at 1 mA load - minimizes quiescent drain in always-on subsystems like real-time clocks or wake-up logic. |
| Shutdown Current | ≤1 µA at 85 °C - supports multi-week standby in battery-backed IoT edge nodes. |
| Thermal Protection | 160 °C junction shutdown with 20 °C hysteresis - prevents permanent damage during sustained overload or poor PCB thermal design. |
| Auto-Discharge | 100 Ω internal NMOS discharge path - clears VOUT within <1 ms after EN deassertion, preventing unintended back-powering. |
Pinout & Package
TSC75-6L package: 1.6 mm × 1.6 mm × 0.55 mm, Pb-free, RoHS-compliant, 6-pin super-thin leaded package with exposed thermal pad (not electrically connected).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - EN | Enable control input | Active-high logic: ≥1.2 V enables regulation; ≤0.4 V disables output and activates auto-discharge. |
| 2 - GND | Power ground reference | Primary thermal path - must connect to large copper plane for 7.6 mW/°C derating above 70 °C ambient. |
| 3 - VIN | Input supply | Accepts 2.2–6 V; requires 1 µF ceramic bypass to GND close to pin for stability and line-transient immunity. |
| 4 - VOUT | Regulated output | Delivers 4.6 V at up to 150 mA; stable with ≥1 µF ceramic output capacitor (ESR < 0.4 Ω). |
| 5 - NC | No connection | Internally unconnected - must remain floating; no routing or soldering required. |
| 6 - BP | Noise bypass terminal | Connects to 10 nF ceramic capacitor to GND to reduce output noise to 60 µV(rms); not used for SiP21107/SiP21108 variants. |
Key Features
| Feature | Design Value |
|---|---|
| Low-noise BP pin architecture | Enables 60 µV(rms) output noise with only 10 nF capacitor - eliminates need for bulky LC filters in RF power rails. |
| Auto-discharge on shutdown | 100 Ω internal NMOS discharges 1 µF output cap in <1 ms - prevents latch-up or false wake-up in multi-rail systems. |
| P-channel MOSFET pass element | 0.9 Ω typical RDS(on) and zero gate drive current - achieves 35 µA ground current and avoids PNP base-current losses. |
| Stable with minimal capacitance | Guaranteed stability with 1 µF ceramic COUT - reduces BOM count and board area vs. legacy LDOs requiring 10–22 µF tantalum. |
| Integrated protection | 330 mA current limit (typ) and 160 °C thermal shutdown - allows safe short-circuit testing and eliminates need for external foldback circuitry. |
Applications
| Cellular Handset Power Rail | Wireless Modem RF Front-End |
|---|---|
Use Scenario: Powers baseband processor I/O or camera sensor in GSM/UMTS handset with single-cell Li-ion (3.0–4.2 V). IC Role / Device Role / Timing Role: Primary 4.6 V LDO delivering clean, low-noise bias to analog front-end and ADC reference circuits. Use Value: 135 mV dropout extends usable battery life by >12 minutes at end-of-discharge; 60 µV(rms) noise prevents SNR degradation in receiver chain. | Use Scenario: Supplies local oscillator (LO) buffer and power amplifier bias in 802.11b/g/n Wi-Fi module. IC Role / Device Role / Timing Role: Low-noise post-regulator for RF synthesizer VCO and mixer stages requiring sub-100 µV ripple. Use Value: BP pin + 10 nF cap achieves noise floor below −120 dBc/Hz at 100 kHz offset - critical for EVM compliance in 64-QAM transmission. |
| Digital Camera Image Sensor Bias | Portable Medical Pulse Oximeter |
Use Scenario: Provides regulated 4.6 V to CMOS image sensor and analog signal chain in compact digital still/video camera. IC Role / Device Role / Timing Role: Fixed-output LDO with fast load-transient response for pixel readout and ADC driver stages. Use Value: Active pull-down circuit improves output recovery time to <5 µs after 100 mA step load - prevents image line corruption during burst capture. | Use Scenario: Powers photodiode transimpedance amplifier and analog front-end in battery-operated pulse oximeter. IC Role / Device Role / Timing Role: Ultra-low-noise, low-quiescent regulator for precision analog measurement path. Use Value: 35 µA ground current at 1 mA load enables >30-day battery life in continuous SpO₂ monitoring mode; 60 µV(rms) noise avoids false saturation in DC-coupled amplifiers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LDO regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MCP1700T-4602E/TT | 250 mA rated, 170 mV dropout at 250 mA, 30 µV(rms) noise, SOT-23-5 package | Larger footprint (3.05 × 2.85 mm), higher max current but no BP pin - requires external RC filter for equivalent noise performance | Select when higher output current headroom is needed and board space permits larger package. |
| NCP1117DT46RKG | 1 A rated, 1.2 V dropout at 800 mA, 45 µV(rms) noise, SOT-223 package | Thermal performance limited by SOT-223; no auto-discharge; requires ≥10 µF output capacitor for stability | Select for high-current industrial applications where PCB area and thermal mass support larger package and higher power dissipation. |
Compared with MCP1700T-4602E/TT and NCP1117DT46RKG, SIP21106DVP-46-E3 delivers superior noise performance per unit area due to its dedicated BP pin, faster transient response via active pull-down, and guaranteed 1 µF ceramic stability - making it optimal for space-constrained, noise-sensitive portable designs.
Availability
SIP21106DVP-46-E3 is available at Aetrix Electronics and suitable for cellular handsets, wireless modems, and digital cameras requiring stable component supply with known end-of-life status and legacy inventory support.
Supply support for SIP21106DVP-46-E3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global leader in discrete semiconductors and passive components, specializing in high-reliability power management ICs and advanced packaging technologies.
The SiP21106 series was designed specifically for ultra-low-noise, low-quiescent-current regulation in portable RF and imaging systems - emphasizing minimal board area, fast transient response, and robust thermal behavior in thin-profile packages.
FAQ
What is the maximum input voltage rating for SIP21106DVP-46-E3?
The absolute maximum input voltage for SIP21106DVP-46-E3 is 6.5 V relative to GND. Operation above 6 V is not recommended; the recommended operating range is 2.2 V to 6 V. Exceeding 6.5 V risks permanent damage, and derating is required above 70 °C ambient due to thermal limits in the TSC75-6L package.
Does SIP21106DVP-46-E3 require an external bypass capacitor on the BP pin?
Yes - SIP21106DVP-46-E3 requires a 10 nF ceramic capacitor connected between the BP pin and GND to achieve its specified 60 µV(rms) output noise performance across the 10 Hz–100 kHz bandwidth. Omitting this capacitor increases noise to ~350 µV(rms), matching the SiP21107/SiP21108 variants. Larger values (>50 nF) are not recommended as they degrade startup time.
How does the auto-discharge function work in SIP21106DVP-46-E3?
When the EN pin is pulled low, SIP21106DVP-46-E3 enters shutdown mode and activates an internal 100 Ω NMOS transistor between VOUT and GND. This path discharges a 1 µF output capacitor to <10 % of nominal voltage in under 1 ms, preventing back-powering of upstream circuitry and ensuring clean power sequencing in multi-rail systems.
Is SIP21106DVP-46-E3 compatible with ceramic output capacitors?
Yes - SIP21106DVP-46-E3 is fully stable with 1 µF X7R or Y7R ceramic output capacitors (ESR < 0.4 Ω). Unlike many legacy LDOs, it does not require tantalum or electrolytic capacitors. Stability is guaranteed across the full −40 °C to +85 °C temperature range when using 1 µF ceramic caps with appropriate dielectric characteristics.
What is the thermal derating behavior of SIP21106DVP-46-E3 in the TSC75-6L package?
SIP21106DVP-46-E3 in the TSC75-6L package has a thermal resistance θJA of 131 °C/W and must be derated at 7.6 mW/°C above 70 °C ambient temperature. Maximum power dissipation drops linearly from 420 mW at 70 °C to 0 mW at 125 °C junction temperature, requiring careful PCB layout with GND plane connection to the GND pin for thermal management.
SIP21106DVP-46-E3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- -
- Package/Case:
- PowerPAK® TSC-75-6
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 6V
- Voltage - Output (Min/Fixed):
- 4.6V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.22V @ 150mA
- Current - Output:
- 150mA
- Current - Quiescent (Iq):
- 85 µA
- Current - Supply (Max):
- -
- PSRR:
- 75dB ~ 40dB (1kHz ~ 100kHz)
- Control Features:
- Enable
- Protection Features:
- Over Temperature, Short Circuit
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- PowerPAK® TSC75-6
SIP21106DVP-46-E3 FAQ
1.How can I place an order for SIP21106DVP-46-E3 through Aetrix?
Please submit a Request for Quotation (RFQ) for SIP21106DVP-46-E3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SIP21106DVP-46-E3 reliable?
The price and inventory of SIP21106DVP-46-E3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SIP21106DVP-46-E3 is usually 5 days.
3.What payment methods are accepted for SIP21106DVP-46-E3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SIP21106DVP-46-E3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SIP21106DVP-46-E3?
SIP21106DVP-46-E3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SIP21106DVP-46-E3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SIP21106DVP-46-E3?
For technical support, including SIP21106DVP-46-E3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SIP21106DVP-46-E3 requirements.
6.How does Aetrix verify that SIP21106DVP-46-E3 is sourced from the original manufacturer or authorized distributors?
All SIP21106DVP-46-E3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SIP21106DVP-46-E3 meets industry standards.
7.What is the process for return or replacement of SIP21106DVP-46-E3?
All SIP21106DVP-46-E3 units undergo pre-shipment inspection (PSI). If there is an issue with SIP21106DVP-46-E3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SIP21106DVP-46-E3 part is unused and in its original packaging.
Return procedure for SIP21106DVP-46-E3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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