Vishay Siliconix SIP21107DR-26-E3
- Part No.:
- SIP21107DR-26-E3
- Manufacturer:
- Vishay Siliconix
- Package:
- 5-TSSOP, SC-70-5, SOT-353
- Datasheet:
-
SIP21107DR-26-E3.pdf
- Description:
- IC REG LINEAR 2.6V 150MA SC70-5
- Quantity:
- Payment:

- Shipping:

Inventory:1,740
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SIP21107DR-26-E3 from Vishay Siliconix is a 2.6 V fixed-output, 150 mA low-dropout linear regulator with Power-OK (POK) error flag output, 135 mV dropout at full load, 1.0 % output voltage accuracy at 25 °C, and operation across -40 °C to +85 °C ambient. It delivers stable, low-noise power for RF-sensitive portable electronics requiring precise enable control and fault monitoring.
For engineers reviewing the SIP21107DR-26-E3 datasheet, SIP21107DR-26-E3 pinout, SIP21107DR-26-E3 application, or SIP21107DR-26-E3 equivalent, key selection criteria include POK threshold behavior (93 % nominal), shutdown current (<1 µA), auto-discharge resistance (100 Ω), thermal protection (160 °C), and compatibility with 1 µF ceramic output capacitors without external compensation.
Technical Context
The SIP21107DR-26-E3 uses an internal P-channel MOSFET pass transistor (0.9 Ω typical RDS(on)) and a 1.2 V bandgap reference to achieve tight regulation. Its error amplifier compares feedback against reference and drives the gate to maintain output within ±2.5 % over full temperature and load range.
The POK function is implemented via an open-drain NMOS comparator monitoring VOUT relative to VIN; it asserts low when VOUT falls below 90–96 % of nominal under-voltage conditions, with 1.5 % hysteresis and 40 µs delay from VOUT transition to POK response.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 2.6 V ±2.5 % over -40 °C to +85 °C; enables direct replacement of 2.6 V logic rails without external resistors. |
| Dropout Voltage | 135 mV at 150 mA load; allows operation from 2.73 V input while maintaining regulation - critical for single-cell Li-ion or alkaline systems. |
| POK Threshold | 93 % nominal VOUT (2.418 V), with 90–96 % guaranteed range; provides reliable power-good signaling before downstream circuitry powers up. |
| Ground Current | 35 µA typical at 1 mA load; minimizes quiescent drain in battery-backed standby modes. |
| Shutdown Current | ≤1 µA maximum at 85 °C; ensures negligible battery leakage during extended sleep states. |
| Auto-Discharge Resistance | 100 Ω typical; discharges 1 µF output capacitor to <100 mV in <1 ms after EN deactivation - prevents residual voltage hold-up. |
| Thermal Shutdown | 160 °C junction activation with 20 °C hysteresis; protects against sustained overload or poor PCB thermal design. |
Pinout & Package
SIP21107DR-26-E3 is packaged in SC70-5L (2.1 mm × 2.1 mm × 0.95 mm), RoHS-compliant, with 5 active terminals and no NC pin in this variant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - EN | Enable input | Active-high logic control; device enabled when ≥1.2 V applied, disabled when ≤0.4 V; must not float - tie to VIN if unused. |
| 2 - GND | Power ground | Primary return path for load current and thermal conduction; requires direct connection to large copper plane for thermal management. |
| 3 - VIN | Input supply | Accepts 2.2–6.0 V input; bypassed with 1 µF ceramic capacitor to minimize line noise and transient impedance. |
| 4 - VOUT | Regulated output | Delivers 2.6 V ±2.5 %; stable with ≥1 µF ceramic output capacitor; supports 330 mA peak current during startup. |
| 5 - POK | Open-drain error flag | Asserts low when VOUT drops below POK threshold; requires external pull-up to VIN or VOUT; sinks ≤0.5 mA. |
Key Features
| Feature | Design Value |
|---|---|
| Noise-bypass capacitor not required | Eliminates need for external 10 nF BP capacitor - simplifies BOM and layout vs. SiP21106 family members. |
| Integrated POK (Power OK) output | Provides system-level power sequencing and fault detection without external comparators or voltage monitors. |
| Output auto-discharge on shutdown | 100 Ω internal NMOS pulls VOUT to ground within 1 ms - prevents unintended wake-up or latch-up in downstream logic. |
| Short-circuit and thermal protection | 330 mA typical current limit and 160 °C thermal shutdown prevent damage during faults - no external foldback circuitry needed. |
| Stable with low-ESR ceramic capacitors | Guaranteed stability with 1 µF X7R/Y7R ceramics; eliminates need for tantalum or aluminum electrolytics - reduces size and cost. |
Applications
| Cellular Handsets | Wireless Modems |
|---|---|
Use Scenario: Powering baseband processor I/O banks and RF front-end bias rails in compact GSM/UMTS handsets. IC Role / Device Role / Timing Role: Primary 2.6 V LDO supplying noise-sensitive analog sections; POK synchronizes boot sequence with PMIC. Use Value: 135 mV dropout extends usable battery range by >15 minutes per charge cycle; POK eliminates boot-time race conditions. | Use Scenario: Regulating 2.6 V supply for LTE modem transceivers and SIM interface circuitry in M2M modules. IC Role / Device Role / Timing Role: Standby-mode LDO with POK-driven reset assertion during brown-out events. Use Value: <1 µA shutdown current enables multi-year battery life in remote sensor nodes; auto-discharge prevents SIM card corruption on power loss. |
| Digital Cameras | Noise-Sensitive RF Systems |
Use Scenario: Supplying image sensor interface and flash controller logic in ultra-thin point-and-shoot cameras. IC Role / Device Role / Timing Role: Secondary LDO delivering clean 2.6 V to high-speed serial interfaces (e.g., MIPI D-PHY). Use Value: 1.0 % initial accuracy ensures compliance with sensor vendor voltage tolerance specs; SC70-5L footprint saves board space. | Use Scenario: Biasing low-noise amplifiers (LNAs) and mixer stages in GPS/Wi-Fi front-ends. IC Role / Device Role / Timing Role: Low-ripple, POK-monitored supply for RF signal chain components requiring strict voltage stability. Use Value: Absence of BP capacitor requirement avoids parasitic resonance; POK enables fast RF subsystem reset upon supply sag. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LDO regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MCP1826-2602E/DB | 2.6 V fixed, 300 mA output, 350 mV dropout at 300 mA, no POK pin, 65 µA quiescent current | Lacks power-good signaling; higher dropout limits use in low-VIN battery systems | Select when higher output current is required and POK is unnecessary; verify thermal derating for SC70-5L footprint. |
| TCS21107DVP-26-E3 | Same SiP21107 family, TSC75-6L package (1.6 mm × 1.6 mm), identical electrical specs, lower thermal resistance (131 °C/W) | Smaller footprint but requires different PCB land pattern; better thermal performance in high-power-density layouts | Select when board space is constrained and thermal margin is critical; validate solder reflow profile for 0.55 mm height. |
Compared with MCP1826-2602E/DB, SIP21107DR-26-E3 offers tighter dropout and integrated POK at lower quiescent current, enabling longer battery life and safer power sequencing. Against TCS21107DVP-26-E3, it trades thermal efficiency for broader distributor availability in SC70-5L form factor.
Availability
SIP21107DR-26-E3 is available at Aetrix Electronics and suitable for cellular handsets, wireless modems, digital cameras, and noise-sensitive RF systems requiring stable component supply despite end-of-life status.
Supply support for SIP21107DR-26-E3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix designs high-performance discrete semiconductors and power ICs focused on efficiency, reliability, and miniaturization for demanding power management applications.
The SiP21107 series was engineered specifically for portable electronics needing low-noise, low-quiescent-current LDOs with integrated power-status monitoring - targeting battery-powered RF and imaging subsystems.
FAQ
What is the POK threshold voltage for SIP21107DR-26-E3?
The POK threshold for SIP21107DR-26-E3 is defined as 93 % of nominal VOUT, i.e., 2.418 V, with a guaranteed range of 90–96 % (2.34–2.496 V) over -40 °C to +85 °C. This threshold is referenced to VIN, and POK goes low when VOUT falls below this level due to dropout, overcurrent, or thermal shutdown. SIP21107DR-26-E3 requires an external pull-up resistor to VIN or VOUT for proper logic-level translation.
Does SIP21107DR-26-E3 require an external bypass capacitor?
No, SIP21107DR-26-E3 does not require an external noise-bypass capacitor - unlike the SiP21106 variant, which needs a 10 nF capacitor on the BP pin. The SIP21107DR-26-E3 integrates internal noise filtering and achieves stable operation with only the standard 1 µF input and output ceramic capacitors. This simplifies layout and reduces BOM count while maintaining 350 µV(rms) output noise (10 Hz–100 kHz).
What is the maximum allowable input voltage for SIP21107DR-26-E3?
The absolute maximum input voltage for SIP21107DR-26-E3 is 6.5 V, but the recommended operating range is 2.2 V to 6.0 V per the datasheet. Operation above 6.0 V risks exceeding safe power dissipation limits, especially in the SC70-5L package (θJA = 294 °C/W). For reliable long-term operation at 6.0 V input with 2.6 V output and 150 mA load, ambient temperature must remain below 55 °C to keep junction temperature below 125 °C.
How does the auto-discharge function work in SIP21107DR-26-E3?
When the EN pin is pulled low, SIP21107DR-26-E3 enters shutdown mode and activates an internal 100 Ω NMOS discharge path between VOUT and GND. This resistor discharges a 1 µF output capacitor from 2.6 V to <100 mV in under 1 ms, preventing residual voltage from powering downstream circuits or causing undefined logic states. The discharge path is automatically disabled when EN returns high, and SIP21107DR-26-E3 resumes regulation with 70 µs turn-on time.
Is SIP21107DR-26-E3 still manufacturable or supported?
SIP21107DR-26-E3 is End of Life (EOL) with last available purchase date of 31-Dec-2014 per Vishay document 74442 Rev. G. However, Aetrix Electronics maintains legacy inventory and offers traceable, tested units with full documentation. For new designs, Vishay recommends evaluating pin-compatible alternatives like the TCS21107DVP-26-E3 (TSC75-6L) or migrating to newer-generation LDOs with enhanced PSRR and lower quiescent current.
SIP21107DR-26-E3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- -
- Package/Case:
- 5-TSSOP, SC-70-5, SOT-353
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 6V
- Voltage - Output (Min/Fixed):
- 2.6V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.22V @ 150mA
- Current - Output:
- 150mA
- Current - Quiescent (Iq):
- 85 µA
- Current - Supply (Max):
- -
- PSRR:
- 72dB ~ 38dB (1kHz ~ 100kHz)
- Control Features:
- Enable, Power Good
- Protection Features:
- Over Temperature, Short Circuit
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SC-70-5
SIP21107DR-26-E3 FAQ
1.How can I place an order for SIP21107DR-26-E3 through Aetrix?
Please submit a Request for Quotation (RFQ) for SIP21107DR-26-E3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SIP21107DR-26-E3 reliable?
The price and inventory of SIP21107DR-26-E3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SIP21107DR-26-E3 is usually 5 days.
3.What payment methods are accepted for SIP21107DR-26-E3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SIP21107DR-26-E3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SIP21107DR-26-E3?
SIP21107DR-26-E3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SIP21107DR-26-E3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SIP21107DR-26-E3?
For technical support, including SIP21107DR-26-E3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SIP21107DR-26-E3 requirements.
6.How does Aetrix verify that SIP21107DR-26-E3 is sourced from the original manufacturer or authorized distributors?
All SIP21107DR-26-E3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SIP21107DR-26-E3 meets industry standards.
7.What is the process for return or replacement of SIP21107DR-26-E3?
All SIP21107DR-26-E3 units undergo pre-shipment inspection (PSI). If there is an issue with SIP21107DR-26-E3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SIP21107DR-26-E3 part is unused and in its original packaging.
Return procedure for SIP21107DR-26-E3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SIP21107DR-26-E3 Tags

-
MIC5504-1.8YM5-TR
Microchip Technology

-
MIC5504-3.3YM5-TR
Microchip Technology

-
MIC5365-3.0YC5-TR
Microchip Technology

-
MIC5365-1.8YC5-TR
Microchip Technology

-
MIC5365-2.5YC5-TR
Microchip Technology

-
MIC5365-3.3YC5-TR
Microchip Technology

-
MIC5365-3.3YD5-TR
Microchip Technology

-
MIC5317-3.3YM5-TR
Microchip Technology

-
TLV1117LV33DCYR
Texas Instruments

-
MIC5317-3.3YMT-TZ
Microchip Technology

-
MIC5528-3.3YMT-TR
Microchip Technology

-
TLV75801PDRVR
Texas Instruments
Tech Hub
Comparator circuit design covering voltage thresholds, input limits, open-collector outputs, LM393 wiring, op-amp differences, hysteresis, timing, window detection and practical fault diagnosis.
Schmitt triggers use separate rising and falling thresholds to stabilize slow or noisy signals. This guide covers hysteresis, 74HC14 and 74HCT14 selection, comparator calculations, RC oscillators and p…
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

