Vishay Siliconix SIP21107DVP-26-E3
- Part No.:
- SIP21107DVP-26-E3
- Manufacturer:
- Vishay Siliconix
- Package:
- PowerPAK® TSC-75-6
- Datasheet:
-
SIP21107DVP-26-E3.pdf
- Description:
- IC REG LIN 2.6V 150MA TSC75-6
- Quantity:
- Payment:

- Shipping:

Inventory:1,669
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Product details
Overview
SIP21107DVP-26-E3 from Vishay Siliconix is a 2.6 V fixed-output, 150 mA low-noise LDO regulator with Power OK (POK) error flag and no external bypass capacitor requirement. It features 135 mV dropout at 150 mA, ±2.5 % output voltage accuracy over -40 °C to +85 °C, 1 µA max shutdown current, and auto-discharge via 100 Ω NMOS during shutdown. It serves as a stable, low-noise supply for RF sections in portable wireless handsets.
For engineers reviewing the SIP21107DVP-26-E3 datasheet, SIP21107DVP-26-E3 pinout, SIP21107DVP-26-E3 application, or SIP21107DVP-26-E3 equivalent, key selection criteria include POK functionality, 2.6 V fixed output, TSC75-6L package compatibility, dropout performance at 150 mA load, and industrial temperature operation without noise-bypass capacitor.
Technical Context
The SIP21107DVP-26-E3 uses an internal P-channel MOSFET pass transistor (0.9 Ω typical RDS(on)) and a 1.2 V bandgap reference to achieve precise regulation. Its error amplifier compares feedback against the reference and drives the gate to maintain output stability under varying load and line conditions.
It integrates open-drain POK logic that asserts low when VOUT falls below 90–96 % of nominal (for 2.6 V output), with 40 µs delay from VOUT to POK transition. Shutdown is controlled by EN pin (VENL ≤ 0.4 V), enabling <1 µA quiescent current and active output discharge through internal 100 Ω NMOS.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 2.6 V ±2.5 % over -40 °C to +85 °C - ensures stable core voltage for baseband ICs in wireless handsets |
| Dropout Voltage | 135 mV at 150 mA load - enables operation down to VIN = 2.73 V while maintaining regulation |
| Ground Current | 35 µA typical at 1 mA load - extends battery runtime in standby mode |
| Shutdown Current | 1 µA maximum at 85 °C - minimizes leakage drain during system sleep |
| POK Threshold | 90–96 % of VOUT (2.34–2.496 V for 2.6 V output) - provides accurate power-good monitoring for sequenced power-up |
| Auto-Discharge Resistance | 100 Ω NMOS - discharges 1 µF output cap to <10 % VOUT in <1 ms upon shutdown |
| Thermal Protection | 160 °C junction shutdown with 20 °C hysteresis - prevents permanent damage during sustained overload |
Pinout & Package
TSC75-6L package: 1.6 mm × 1.6 mm × 0.55 mm, Pb-free, RoHS-compliant, 6-pin leadless surface-mount.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (EN) | Enable input | Active-high control; <0.4 V disables regulator and triggers auto-discharge |
| 2 (GND) | Power ground | Primary thermal path; must connect to large PCB ground plane for thermal derating |
| 3 (VIN) | Input supply | Accepts 2.2–6.0 V; requires 1 µF ceramic bypass to GND near pin |
| 4 (VOUT) | Regulated output | Delivers 2.6 V up to 150 mA; stable with ≥1 µF ceramic output capacitor |
| 5 (NC) | No connection | Not internally bonded; leave unconnected on PCB |
| 6 (POK) | Open-drain error flag | Active-low signal requiring external pull-up to VIN or VOUT; indicates VOUT fault |
Key Features
| Feature | Design Value |
|---|---|
| Integrated POK with programmable threshold | Enables reliable power sequencing and fault detection without external comparator circuitry |
| No external noise-bypass capacitor required | Reduces BOM count and board area versus SiP21106 variants needing 10 nF BP cap |
| Auto-discharge via internal 100 Ω NMOS | Eliminates need for external discharge FET or resistor network during shutdown |
| Stable with low-ESR ceramic capacitors | Supports compact 1 µF X7R/X5R output caps - avoids bulkier tantalum or electrolytic solutions |
| Short-circuit protection (330 mA typical) | Allows indefinite output short without damage - simplifies system-level fault tolerance design |
Applications
| Cellular Baseband Power | Wireless Modem Core Supply |
|---|---|
Use Scenario: Powering baseband processor core in dual-mode GSM/UMTS handset with tight battery voltage margin. IC Role / Device Role / Timing Role: Primary 2.6 V LDO delivering regulated supply to processor I/O and memory interface. Use Value: 135 mV dropout enables >90 % battery utilization down to 2.73 V input; POK confirms rail readiness before processor boot. | Use Scenario: Supplying 2.6 V to LTE modem RF transceiver digital section where noise coupling must be minimized. IC Role / Device Role / Timing Role: Low-noise, fixed-output LDO with POK signaling used for clean digital domain power. Use Value: No BP capacitor needed eliminates potential noise injection path; POK synchronizes modem initialization with rail stability. |
| Digital Camera Image Processor | PDA Application Processor Rail |
Use Scenario: Providing 2.6 V to image signal processor (ISP) in compact digital camera with aggressive size constraints. IC Role / Device Role / Timing Role: Compact-area LDO in TSC75-6L package powering ISP core logic and ADC interface. Use Value: 1.6 mm × 1.6 mm footprint saves board space; auto-discharge prevents residual charge from interfering with fast power cycling. | Use Scenario: Delivering 2.6 V to ARM-based application processor in handheld PDA with multi-rail sequencing requirements. IC Role / Device Role / Timing Role: Sequenced enable-controlled LDO with POK output feeding processor power-good input. Use Value: EN/POK pins support deterministic power-up order; ±2.5 % accuracy ensures compliance with processor VDD tolerance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LDO regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AP2112K-2.6TRG1 | 2.6 V fixed, 600 mA output, SOT-23-5, no POK, higher quiescent current (65 µA typ) | Lacks POK flag and auto-discharge; suited for non-sequenced, higher-current rails | Select only if POK and discharge are unnecessary and higher output current is required |
| MCP1700T-2602E/TT | 2.6 V fixed, 250 mA, SOT-23-5, no POK, 1.6 µA shutdown current, 600 mV dropout at 250 mA | Higher dropout limits usable input range; no POK removes fault-monitoring capability | Choose only for cost-sensitive, non-critical rails where sequencing and ultra-low dropout are not required |
Compared with AP2112K-2.6TRG1 and MCP1700T-2602E/TT, SIP21107DVP-26-E3 uniquely combines POK flag, 100 Ω auto-discharge, 135 mV dropout at 150 mA, and TSC75-6L footprint - making it optimal for space-constrained, sequenced, battery-powered RF systems.
Availability
SIP21107DVP-26-E3 is available at Aetrix Electronics and suitable for cellular phones, wireless modems, and digital cameras requiring stable component supply despite end-of-life status.
Supply support for SIP21107DVP-26-E3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix designs high-performance discrete semiconductors and integrated power solutions, emphasizing reliability, efficiency, and miniaturization for demanding electronic systems.
The SiP21107 series was developed specifically for low-power, noise-sensitive portable applications requiring integrated power-good signaling and minimal external components - targeting RF front-ends and baseband subsystems in wireless handsets.
FAQ
What is the POK threshold voltage for SIP21107DVP-26-E3?
The POK threshold for SIP21107DVP-26-E3 is specified as 90–96 % of nominal VOUT, translating to 2.34–2.496 V for its 2.6 V output. POK goes low when VOUT drops below this window and returns high after recovery with hysteresis. This behavior is confirmed in the device's Electrical Characteristics table and timing waveforms in Document Number 74442.
Does SIP21107DVP-26-E3 require an external bypass capacitor?
No, SIP21107DVP-26-E3 does not require an external noise-bypass capacitor - unlike the SiP21106 variant. Its internal architecture eliminates the need for a BP pin capacitor, reducing component count and PCB area. This is explicitly stated in the product description and functional block diagram of Document Number 74442.
What is the maximum allowable input voltage for SIP21107DVP-26-E3?
The absolute maximum input voltage for SIP21107DVP-26-E3 is 6.5 V, but the recommended operating range is 2.2 V to 6.0 V. Operation above 6.0 V risks exceeding safe power dissipation limits, especially in the TSC75-6L package, which has a 420 mW power rating at 70 °C ambient.
How does the auto-discharge function work in SIP21107DVP-26-E3?
When EN is pulled low, SIP21107DVP-26-E3 activates an internal 100 Ω NMOS between VOUT and GND, discharging a 1 µF output capacitor to <10 % of VOUT in under 1 ms. This eliminates residual voltage that could interfere with system reset or cause latch-up in downstream logic - a feature confirmed in the DETAILED DESCRIPTION section of Document Number 74442.
Is SIP21107DVP-26-E3 still in production?
No, SIP21107DVP-26-E3 is End of Life with last available purchase date of 31-Dec-2014 per Vishay documentation. However, Aetrix Electronics maintains legacy inventory and supports continuity programs including traceable sourcing and lifecycle coordination for ongoing production needs.
SIP21107DVP-26-E3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- -
- Package/Case:
- PowerPAK® TSC-75-6
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 6V
- Voltage - Output (Min/Fixed):
- 2.6V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.22V @ 150mA
- Current - Output:
- 150mA
- Current - Quiescent (Iq):
- 85 µA
- Current - Supply (Max):
- -
- PSRR:
- 72dB ~ 38dB (1kHz ~ 100kHz)
- Control Features:
- Enable, Power Good
- Protection Features:
- Over Temperature, Short Circuit
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- PowerPAK® TSC75-6
SIP21107DVP-26-E3 FAQ
1.How can I place an order for SIP21107DVP-26-E3 through Aetrix?
Please submit a Request for Quotation (RFQ) for SIP21107DVP-26-E3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SIP21107DVP-26-E3 reliable?
The price and inventory of SIP21107DVP-26-E3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SIP21107DVP-26-E3 is usually 5 days.
3.What payment methods are accepted for SIP21107DVP-26-E3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SIP21107DVP-26-E3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SIP21107DVP-26-E3?
SIP21107DVP-26-E3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SIP21107DVP-26-E3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SIP21107DVP-26-E3?
For technical support, including SIP21107DVP-26-E3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SIP21107DVP-26-E3 requirements.
6.How does Aetrix verify that SIP21107DVP-26-E3 is sourced from the original manufacturer or authorized distributors?
All SIP21107DVP-26-E3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SIP21107DVP-26-E3 meets industry standards.
7.What is the process for return or replacement of SIP21107DVP-26-E3?
All SIP21107DVP-26-E3 units undergo pre-shipment inspection (PSI). If there is an issue with SIP21107DVP-26-E3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SIP21107DVP-26-E3 part is unused and in its original packaging.
Return procedure for SIP21107DVP-26-E3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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