Infineon Technologies SLB9645TT12FW13333XUMA2

Overview

SLB9645TT12FW13333XUMA2 from Infineon is a TPM 1.2-compliant Trusted Platform Module in PG-TSSOP-28-2 package, implementing secure boot, cryptographic key storage, and platform integrity verification via I²C interface. It delivers 24 PCRs, 6 kB free NV memory, and low standby current (150 μA typ.) for Chromebook-certified endpoint security. Used in laptop BIOS authentication and firmware attestation chains.

For engineers reviewing the SLB9645TT12FW13333XUMA2 datasheet, SLB9645TT12FW13333XUMA2 pinout, SLB9645TT12FW13333XUMA2 application, or SLB9645TT12FW13333XUMA2 equivalent, key selection criteria include I²C timing compliance (100/400 kHz), DAVINT# interrupt-driven response handling, physical presence (PP) pin hardware control, and -20°C to +85°C operational range.

Technical Context

This device implements the TPM Main Specification v1.2 Rev. 116 with dedicated hardware accelerators for SHA-1, RSA-2048 signing/verification, and HMAC operations. Its I²C interface supports Standard Mode (100 kHz) and Fast Mode (400 kHz), with open-drain SDA/SCL pins requiring external pull-ups.

The module integrates 8 monotonic counters, 1280-byte I/O buffer, and supports up to 10 concurrent sessions with eight 2048-bit keys in volatile storage. Reset is asynchronous and active-low via RESET#, while DAVINT# provides edge-triggered interrupt signaling for response availability without polling.

Key Specifications

Pinout & Package

SLB9645TT12FW13333XUMA2 uses the PG-TSSOP-28-2 surface-mount package (6.1 mm × 12.5 mm, 0.65 mm pitch), optimized for high-density laptop motherboard layouts with thermal pad grounding.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar TPM 1.2 security applications.

Compared with SLB9645XT1.2, this part trades extended temperature tolerance for lower cost and qualification scope; versus ST33TPHF2ESB1, it offers native I²C support and larger NV memory but requires different host driver stack and PCB layout.

Availability

SLB9645TT12FW13333XUMA2 is available at Aetrix Electronics and suitable for laptop manufacturing, industrial controller production, and medical device certification requiring stable component supply and long-term lifecycle assurance.

Supply support for SLB9645TT12FW13333XUMA2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor manufacturer specializing in security, power management, and automotive ICs, with global R&D centers and ISO/IEC 27001-certified security development processes.

This device belongs to the OPTIGA™ TPM product line, designed specifically for hardware-rooted trust in resource-constrained endpoints - prioritizing low-power operation, certified cryptographic primitives, and seamless OS integration.

FAQ

Is SLB9645TT12FW13333XUMA2 compatible with TPM 2.0 software stacks?

No. This device implements only TPM Main Specification v1.2 Rev. 116 and lacks the algorithm agility, ECC support, and command structure required by TPM 2.0. Software drivers must use TCG TPM 1.2 libraries (e.g., trousers, tpm-tools) and cannot be upgraded to 2.0 without hardware replacement.

What is the function of the PP (Physical Presence) pin, and how should it be connected?

The PP pin enables hardware-gated privileged commands such as TPM_ForceClear. When tied to GND (default), those commands are disabled. Connecting it to VDD activates them. The pin has no internal pull-up/down, so unused PP must be fixed to GND or VDD - never left floating - to avoid leakage current and undefined behavior.

Does SLB9645TT12FW13333XUMA2 support both Standard and Fast Mode I²C speeds simultaneously?

Yes. The I²C interface automatically adapts to host clock frequency: it operates at up to 100 kHz in Standard Mode and up to 400 kHz in Fast Mode. No configuration register setting is needed; timing compliance is handled in hardware per Section 4.6 of the datasheet.

How is the 1280-byte I/O buffer utilized during command-response transactions?

The buffer holds complete TPM command packets (up to 1280 bytes) and corresponding responses. Host reads are burst-capable: after DAVINT# asserts, the host can sequentially read the full response without reissuing start conditions, reducing I²C transaction overhead and improving throughput for multi-block operations like PCR reads.