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Infineon Technologies SLB9665VQ20FW560XUMA2
- Part No.:
- SLB9665VQ20FW560XUMA2
- Manufacturer:
- Infineon Technologies
- Category:
- Application Specific Microcontrollers
- Package:
- 32-VFQFN Exposed Pad
- Datasheet:
-
SLB9665VQ20FW560XUMA2.pdf
- Description:
- SECURITY IC'S/AUTHENTICATION IC'
- Quantity:
- Payment:
- Shipping:
Inventory:2,835
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Product details
Overview
SLB9665VQ20FW560XUMA2 from Infineon is a TPM 2.0 Trusted Platform Module compliant with TCG Main Specification v01.16 Level 00, featuring LPC interface, NIST SP800-90A RNG, 24 PCRs (SHA-1/SHA-256), 7206 Byte NV memory, and low standby current (150 µA typ.) for secure boot and platform attestation in x86-based PCs and Chromebooks.
For engineers reviewing the SLB9665VQ20FW560XUMA2 datasheet, SLB9665VQ20FW560XUMA2 pinout, SLB9665VQ20FW560XUMA2 application, or SLB9665VQ20FW560XUMA2 equivalent, key selection criteria include LPC timing compliance, EK personalization support, temperature range (-20°C to +85°C), I/O buffer size (1280 Byte), and persistent object capacity (7 loaded).
Technical Context
The SLB9665VQ20FW560XUMA2 implements a dedicated TPM 2.0 stack with locality-based LPC access control, supporting only TPM-type read/write cycles-not legacy IO-mapped accesses. It enforces strict register-level access rights per ACTIVE.LOCALITY state, rejecting unauthorized cycles via master abort without SYNC generation.
Power management is fully autonomous: the device wakes on LPC command activity and returns to 150 µA standby mode within 50 ms after last command completion-no external LPCPD or CLKRUN signals required. All cryptographic operations execute in hardened internal firmware with no host-side driver dependency beyond Linux kernel 3.10+ built-in tpm_tis_lpc support.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| TPM Specification | TCG TPM Main Spec v01.16 Level 00 - defines mandatory commands, PCR policies, and authorization logic for certified platform qualification. |
| LPC Interface | Low Pin Count bus with TPM-type cycle support only - requires host LPC controller configured for locality-aware access, no IO port mapping. |
| Temperature Range | -20°C to +85°C standard grade - validated for desktop, notebook, and industrial edge compute platforms without extended thermal derating. |
| Standby Current | 150 µA typical - enables battery-backed security persistence in always-on systems without compromising runtime budget. |
| NV Memory Size | 7206 Bytes - sufficient for EK certificate, platform-specific keys, sealed data blobs, and policy-managed credentials across multiple boot sessions. |
| PCR Count | 24 Platform Configuration Registers - supports SHA-1 and SHA-256 hashing for measured boot chains covering BIOS, bootloader, OS loader, and hypervisor components. |
| I/O Buffer | 1280 Byte - accommodates full TPM2_Commit, TPM2_PolicySecret, or multi-part NV_Write commands without segmentation overhead. |
Pinout & Package
SLB9665VQ20FW560XUMA2 uses PG-VQFN-32-13 package: 5 mm × 5 mm body, 0.5 mm pitch, exposed thermal pad, 32 terminals, RoHS-compliant matte tin finish. Pinout conforms to Figure 2 of Infineon DS Rev 1.2 (2018).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| LCLK | LPC Clock Input | Accepts 33 MHz host LPC clock; synchronous timing reference for all TPM-type transactions and internal state machine sequencing. |
| LRESET# | Active-Low Reset | Asynchronous hardware reset; initiates cold start sequence including RNG reseeding and EK validation-timing defined in Figure 4 (tRSTH ≥ 100 ns). |
| LFRAME# | LPC Frame Strobe | Indicates start of LPC cycle; must be asserted before LAD[3:0] valid; used by TPM to detect locality and cycle type (read/write). |
| LAD[3:0] | LPC Address/Data Bus | Multiplexed bidirectional bus carrying address (during FRAME# high) and data (during FRAME# low); supports 4-bit nibble transfers per cycle. |
| LDRQ# | LPC DMA Request | Not used - SLB9665VQ20FW560XUMA2 does not implement DMA; pin is NC per Table 6 and must be left unconnected. |
| VDD | Core Power Supply | 3.3 V ±10% supply; powers digital logic, crypto engine, and SRAM; decoupling capacitor (100 nF) required within 5 mm of pin. |
| VSS | Digital Ground | Reference for all digital I/O; must be connected to system ground plane with low-inductance path to minimize noise coupling into LPC signaling. |
| EPAD | Thermal Pad | Internally connected to die substrate; must be soldered to PCB thermal pad (≥ 10 mm²) for reliable junction temperature control under sustained crypto load. |
Key Features
| Feature | Design Value |
|---|---|
| Endorsement Key Personalization | Factory-provisioned unique ECC P-256 EK with X.509 certificate - enables hardware-rooted identity binding and attestation without host-side key generation. |
| Secure Random Number Generation | NIST SP800-90A compliant deterministic RNG using on-die entropy source - required for TPM2_CreatePrimary, TPM2_StirRandom, and session key derivation. |
| PCR Flexibility | 24 PCRs configurable as SHA-1 or SHA-256 - allows coexistence of legacy BIOS measurement logs and modern UEFI Secure Boot attestations in same module. |
| Session Management | Supports up to 64 active sessions and 3 loaded transient objects - enables concurrent policy evaluation, authorization chaining, and multi-step key unwrapping workflows. |
| Linux Kernel Integration | Built-in support since kernel v3.10 via tpm_tis_lpc driver - eliminates need for proprietary firmware or user-space daemons for basic TPM2 commands. |
Applications
| Desktop PC Security | Chromebook Platform Attestation |
|---|---|
|
Use Scenario: Host BIOS performs measured boot, extending PCRs with firmware hash values before loading OS. IC Role / Device Role / Timing Role: TPM 2.0 root-of-trust executing PCR extension, quote generation, and EK-based attestation during pre-boot phase. Use Value: Enables remote verification that boot chain remains unmodified-critical for enterprise endpoint compliance and zero-trust network access. |
Use Scenario: Chromebook verifies firmware integrity at power-on and reports health status to Google's Verified Boot service. IC Role / Device Role / Timing Role: Dedicated TPM managing firmware signing keys, sealing recovery images, and generating attestation quotes for cloud validation. Use Value: Meets Google ChromeOS certification requirements for hardware-enforced verified boot and tamper-evident recovery. |
| Industrial Edge Compute | Thin Client Authentication |
|
Use Scenario: Fanless industrial PC boots Linux RTOS and validates signed firmware updates before execution. IC Role / Device Role / Timing Role: Secure storage for update signature keys and runtime PCR logging of kernel modules and device drivers. Use Value: Prevents unauthorized firmware modification in unattended deployments where physical access cannot be guaranteed. |
Use Scenario: Zero-client terminal authenticates to corporate VDI server using TPM-bound credentials instead of password-based tokens. IC Role / Device Role / Timing Role: Persistent storage of asymmetric keys for TLS client authentication and session resumption without credential caching. Use Value: Eliminates password replay risks and enables FIDO2-style phishing-resistant login tied to hardware identity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar TPM 2.0 security module applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SLB9670VQ20FW560XUMA2 | Enhanced temp range (-40°C to +85°C); identical LPC interface and firmware feature set. | Required for outdoor kiosks or automotive infotainment where ambient exceeds -20°C. | Select when extended thermal operation is mandated; otherwise SLB9665VQ20FW560XUMA2 offers cost-optimized standard-grade performance. |
| ST33TPHF2ESPI | eSPI interface instead of LPC; 3.3 V only; supports TPM 2.0 but lacks Intel TXT certification. | Suitable for newer motherboards with eSPI-native chipset support, not LPC legacy platforms. | Choose only if host platform replaces LPC with eSPI; not drop-in compatible due to protocol and pinout differences. |
Compared with SLB9670VQ20FW560XUMA2 and ST33TPHF2ESPI, SLB9665VQ20FW560XUMA2 delivers certified LPC-based TPM 2.0 functionality at standard temperature grade-ideal for cost-sensitive, volume desktop and Chromebook designs requiring Intel TXT and Windows attestation compliance.
Availability
SLB9665VQ20FW560XUMA2 is available at Aetrix Electronics and suitable for desktop PC security, Chromebook platform attestation, and industrial edge compute requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for security-critical BOMs.
Supply support for SLB9665VQ20FW560XUMA2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Infineon Technologies AG is a German semiconductor manufacturer specializing in security, power management, and automotive ICs, with global manufacturing and quality certifications including ISO/IEC 27001 for secure element development.
The OPTIGA™ TPM product line delivers certified, pre-personalized trusted execution environments for platform integrity-designed specifically for integration into x86 and ARM-based endpoints requiring hardware-rooted identity and attestation.
FAQ
Is SLB9665VQ20FW560XUMA2 pin-compatible with SLB9660?
Yes, SLB9665VQ20FW560XUMA2 is explicitly pin-compatible with SLB9660 per Infineon's datasheet Key Features section. This enables drop-in replacement in existing LPC-based designs without PCB revision, preserving layout, routing, and decoupling while upgrading to TPM 2.0 compliance and enhanced crypto capabilities.
Does SLB9665VQ20FW560XUMA2 support SHA-256 PCR banks?
Yes, it supports 24 PCRs configurable for either SHA-1 or SHA-256 hashing per TCG specification. The firmware enables simultaneous use of both algorithms-e.g., SHA-1 for legacy BIOS measurements and SHA-256 for UEFI Secure Boot-without performance penalty or bank conflict.
What is the maximum NV write size per transaction?
The maximum NV write size is 768 bytes per TPM2_NV_Write command, as specified in the datasheet Section 4.3 DC Characteristics. This limit ensures atomicity and wear-leveling across the 7206-byte NV memory space, preventing partial writes during power loss or interrupt conditions.
Can SLB9665VQ20FW560XUMA2 operate without external reset assertion?
Yes-it supports automatic wake-on-LPC activity and self-managed reset sequencing. While LRESET# is provided for hardware-initiated cold start, the device recovers from sleep autonomously upon LFRAME# assertion, eliminating need for external reset supervisor circuits in most implementations.
SLB9665VQ20FW560XUMA2 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Infineon Technologies
- Series:
- OPTIGA™ TPM
- Package/Case:
- 32-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Not For New Designs
- Programmable:
- Not Verified
- Applications:
- Trusted Platform Module (TPM)
- Core Processor:
- 16-Bit
- Program Memory Type:
- NVM (7.04kB)
- Controller Series:
- -
- RAM Size:
- -
- Interface:
- LPC
- Number of I/O:
- 1
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- -20°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- PG-VQFN-32-13
SLB9665VQ20FW560XUMA2 FAQ
1.How can I place an order for SLB9665VQ20FW560XUMA2 through Aetrix?
Please submit a Request for Quotation (RFQ) for SLB9665VQ20FW560XUMA2 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SLB9665VQ20FW560XUMA2 reliable?
The price and inventory of SLB9665VQ20FW560XUMA2 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SLB9665VQ20FW560XUMA2 is usually 5 days.
3.What payment methods are accepted for SLB9665VQ20FW560XUMA2?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SLB9665VQ20FW560XUMA2 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SLB9665VQ20FW560XUMA2?
SLB9665VQ20FW560XUMA2 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SLB9665VQ20FW560XUMA2 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SLB9665VQ20FW560XUMA2?
For technical support, including SLB9665VQ20FW560XUMA2 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SLB9665VQ20FW560XUMA2 requirements.
6.How does Aetrix verify that SLB9665VQ20FW560XUMA2 is sourced from the original manufacturer or authorized distributors?
All SLB9665VQ20FW560XUMA2 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SLB9665VQ20FW560XUMA2 meets industry standards.
7.What is the process for return or replacement of SLB9665VQ20FW560XUMA2?
All SLB9665VQ20FW560XUMA2 units undergo pre-shipment inspection (PSI). If there is an issue with SLB9665VQ20FW560XUMA2, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SLB9665VQ20FW560XUMA2 part is unused and in its original packaging.
Return procedure for SLB9665VQ20FW560XUMA2:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SLB9665VQ20FW560XUMA2 Tags
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