Infineon Technologies SLE 66C44PE MFC5.6

Overview

SLE 66C44PE MFC5.6 from Infineon Technologies is an 8/16-bit security controller IC for smart card applications, featuring a 0.22 µm CMOS ECO2000 CPU, 68-Kbyte ROM, 2304-Byte RAM (256-byte IRAM + 2048-byte XRAM), 4-Kbyte MicroSlim-EEPROM, and dual-key Triple DES hardware accelerator. It supports ISO/IEC 7816 T=0/T=1 protocols, operates across 1.8 V/3.0 V/5.0 V supply, and delivers up to 33 MHz internal clock via PLL (×1–×4) for EMV-compliant payment, ID, and loyalty cards.

For engineers reviewing the SLE 66C44PE MFC5.6 datasheet, SLE 66C44PE pinout, SLE 66C44PE application in UICC/GSM or EMV payment systems, or SLE 66C44PE equivalent for CC EAL5+-certifiable secure controllers, this page provides verified technical context, memory mapping, cryptographic timing data, power-constrained operation modes, and certified security architecture details.

Technical Context

The SLE 66C44PE implements a dedicated 8/16-bit ECO2000 core with SAB 8051 opcode compatibility and enhanced instructions enabling direct physical memory access beyond 64 KB-up to 16 MB on request. Its Memory Management and Protection Unit (MMU) enforces strict OS/application mode separation using 16 configurable descriptors and supports secure multi-application download post-personalization.

Security execution relies on integrated hardware modules: Dual-Key Triple DES accelerator (3.5 µs encryption at 33 MHz), True Random Number Generator with firmware test, CRC-16 engine per ISO/IEC 3309, and active shield with voltage/frequency/light/glitch/temperature sensors plus UMSLC life-test function-all aligned to planned Common Criteria EAL5+ and VISA Level 3 certification.

Key Specifications

Pinout & Package

Package: Die (unsawn/wire-bonded M5 module form factor for embedding in plastic smart cards; no leaded package).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar security controller applications.

Compared with SLE 66C84PE, the SLE 66C44PE trades memory headroom for die size and cost efficiency in volume EMV/GSM deployments; versus JCOP41, it delivers deterministic crypto latency and lower power at the expense of Java runtime flexibility-making it optimal for native-code, latency-sensitive secure transactions.

Availability

SLE 66C44PE MFC5.6 is available at Aetrix Electronics and suitable for EMV payment terminals, GSM/UICC SIM card manufacturing, and government eID programs requiring stable component supply, long-lifecycle assurance, and certified security architecture.

Supply support for SLE 66C44PE MFC5.6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies AG is a German semiconductor manufacturer specializing in security ICs, power management, and automotive electronics, with global R&D centers and ISO/IEC 27001-certified development processes.

The SLE 66C44PE belongs to Infineon's SLE 66PE security controller product line, engineered specifically for contact smart cards requiring CC EAL5+-aligned hardware security, low-power operation under GSM/UICC constraints, and native-code execution efficiency for EMV migration and multi-application deployment.

FAQ

What is the maximum internal clock frequency and how is it generated?

The SLE 66C44PE achieves up to 33 MHz internal clock frequency using an on-chip PLL that multiplies the external clock (1–7.5 MHz) by factors of ×1, ×2, ×3, or ×4. Frequency selection is programmable in firmware and can be auto-adjusted to maintain fixed power consumption-critical for GSM-compliant current limits. This eliminates need for external high-frequency crystals while preserving timing determinism for cryptographic operations.

Does the SLE 66C44PE support ISO/IEC 7816-3 T=1 protocol with hardware assist?

Yes-the integrated UART fully supports ISO/IEC 7816-3 T=1 block transmission, including automatic checksum generation (LRC), block sequencing, and retransmission handling. All parameters-including character delay, guard time, and wait time extension-are software-configurable. Hardware acceleration is not applied to T=1 framing itself, but DDES and CRC modules offload crypto and integrity tasks during T=1 data exchange.

How is memory protection enforced between OS and application code?

Memory protection is implemented via the hardware Memory Management and Protection Unit (MMU), which uses 16 programmable descriptors to define read/write/execute permissions per memory segment. The OS runs in system mode with full access; applications run in user mode with MMU-enforced restrictions. Code execution from XRAM is permitted, and segments can be dynamically reconfigured-enabling secure post-personalization app loading without compromising existing keys or OS integrity.

What certifications does the SLE 66C44PE target and what security features enable them?

The SLE 66C44PE targets Common Criteria EAL5+ (BSI-PP-0002), VISA Level 3, and EMV 2000 certification. Key enablers include: hardware dual-key Triple DES accelerator with isolated key paths; True RNG with UMSLC life-test; active shield with attack detection; sparkling SFR encryption; voltage/frequency/light/glitch/temperature sensors; and bus confusion logic. These features collectively address side-channel, fault-injection, and physical probing threats defined in CC Protection Profiles.