Analog Devices Inc. 131191-HMC960LP4E
- Part No.:
- 131191-HMC960LP4E
- Manufacturer:
- Analog Devices Inc.
- Category:
- RF, RFID, Wireless Evaluation Boards
- Package:
- Datasheet:
-
131191-HMC960LP4E.pdf
- Description:
- BOARD EVAL VGA HMC960
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
HMC960LP4E from Analog Devices is a dual-channel digitally programmable variable gain amplifier (VGA) for baseband I/Q signal processing, delivering 0–40 dB gain in precise 0.5 dB steps, 6 dB noise figure at 100 Ω input, +30 dBm output IP3, and DC–100 MHz bandwidth - deployed as an ADC driver in direct-conversion transceivers.
For engineers reviewing the HMC960LP4E datasheet, HMC960LP4E pinout, HMC960LP4E application, or HMC960LP4E equivalent, key selection criteria include quadrature channel balance (±0.02 dB gain / ±0.15° phase error), externally adjustable output common-mode voltage, SPI/parallel gain control interface, and 400 Ω or 100 Ω programmable differential input impedance.
Technical Context
The HMC960LP4E implements a three-stage gain architecture with input match/gain stage, resistor-ratio-based second stage (0.5 dB step precision), and differential class-AB output driver with 0/10 dB selectable gain. Gain decoding logic optimizes noise figure by allocating gain across stages based on setting.
It supports two bias configurations: standard (op-amp bias '01', driver bias '01') and high-linearity (driver bias '10'), enabling trade-offs between OIP3 (+32 to +33 dBm) and power consumption (70 mA total supply current). Common-mode output level is set via dedicated CMI/CMQ pins, independent of gain state.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Gain Range | 0 to 40 dB - fully programmable in 0.5 dB increments for fine AGC resolution |
| Signal Bandwidth | DC to 100 MHz (3 dB) - supports wideband baseband I/Q signals up to LTE/WiMAX channel bandwidths |
| Noise Figure | 6 dB at 40 dB gain, 100 Ω input - enables high-sensitivity receiver front-end design |
| Output IP3 | +32 to +33 dBm - maintains linearity under multi-tone interference in dense RF environments |
| I/Q Channel Balance | ±0.02 dB gain / ±0.15° phase error at 20 MHz - ensures <55 dB sideband rejection for clean quadrature demodulation |
| Supply Voltage | 4.5 V to 5.5 V - compatible with standard 5 V industrial and telecom power rails |
| Digital Interface | SPI (up to 30 MHz) and 7-bit parallel (GC[6:0]) - supports real-time gain updates or register-based configuration |
Pinout & Package
Package: 24-lead 4 mm × 4 mm LFCSP (CP-24-16), RoHS-compliant, exposed thermal paddle, MSL1, 0.85 mm height.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (CMQ) | Q-channel output common-mode control | Externally sets Q-output DC offset (1–3 V range); decouples gain setting from output level |
| 2–3 (OQN, OQP) | Q-channel differential outputs | Drive ADC inputs directly; support 400 Ω or 100 Ω differential loads |
| 4–10 (GC[6:0]) | Parallel gain control inputs | 7-bit binary code selects 0–40 dB gain in 0.5 dB steps; supports real-time AGC |
| 11 (DVDD) | Digital supply | 5 V ±10% digital rail; requires local 0.1 µF decoupling to ground |
| 12–14 (SCLK, SDI, SEN) | SPI clock, data-in, enable | Four-wire SPI interface; SEN active-low; SCLK up to 30 MHz |
| 13 (SDO) | SPI data-out | Tri-state output; returns register contents during read cycles |
| 16–17 (OIP, OIN) | I-channel differential outputs | Matched to OQP/OQN for I/Q path symmetry; same drive capability |
| 18 (CMI) | I-channel output common-mode control | Independent of CMQ; enables asymmetric common-mode setup per channel |
| 19–20 (IIP, IIN) | I-channel differential inputs | Programmable 100 Ω or 400 Ω differential input impedance |
| 21 (VDDI) | I-channel analog supply | 5 V ±10% analog rail for I-path; separate from Q-path for PSRR isolation |
| 22 (VDDQ) | Q-channel analog supply | 5 V ±10% analog rail for Q-path; enables independent power domain management |
| 23–24 (IQN, IQP) | Q-channel differential inputs | Matched to IIP/IIN; full differential signal routing required for balance |
Key Features
| Feature | Design Value |
|---|---|
| Glitch-free gain transitions | Eliminates transient output spikes during gain changes - critical for zero-disturbance AGC in burst-mode receivers |
| Programmable input impedance | 100 Ω or 400 Ω differential - simplifies matching to preceding filter or mixer without external resistors |
| Externally controlled output common mode | Independent CMI/CMQ pins allow dynamic alignment to ADC input range - avoids clipping or headroom loss |
| Matched I/Q gain and phase paths | ±0.02 dB / ±0.15° tolerance over 0–100 MHz - enables >55 dB sideband suppression without calibration |
| Two-stage bias optimization | Selectable op-amp/driver bias settings - trades off linearity (OIP3 +33 dBm) vs. power (70 mA typical) |
Applications
| Baseband ADC Driver | Direct-Conversion Transceiver |
|---|---|
Use Scenario: Driving the differential inputs of high-speed ADCs such as the HMCAD1520 (12-bit, 320 MSPS) in software-defined radio systems. IC Role / Device Role / Timing Role: Final gain stage and interface conditioner between analog baseband and digitization; provides precise amplitude scaling and common-mode alignment. Use Value: Eliminates need for external AC-coupling or level-shifting circuitry; 400 Ω output drive matches typical ADC input impedance directly. | Use Scenario: I/Q signal conditioning in LTE/WiFi base station receivers where image rejection and SNR preservation are critical. IC Role / Device Role / Timing Role: Dual-channel VGA in the baseband section after quadrature downconversion; enables adaptive gain control per channel. Use Value: Maintains <0.15° I/Q phase imbalance across 0–100 MHz, ensuring >55 dB sideband rejection without post-processing calibration. |
| Diversity Receiver Front-End | Adaptive Gain Control Loop |
Use Scenario: Simultaneous amplification of independently received I/Q streams in MIMO or antenna diversity architectures. IC Role / Device Role / Timing Role: Matched dual VGA providing identical gain/phase response across parallel RF paths. Use Value: Enables coherent combining of signals with <0.02 dB gain mismatch - preserves diversity gain and EVM performance. | Use Scenario: Closed-loop automatic gain control in test equipment or broadband spectrum analyzers requiring fast, stable amplitude regulation. IC Role / Device Role / Timing Role: Programmable gain element with glitch-free transitions and SPI feedback interface. Use Value: 0.5 dB gain step resolution and <250 µs soft-reset enable sub-dB closed-loop convergence without output disturbance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel VGA applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| HMC900LP5E | Single-channel, 0–30 dB gain, 100 MHz BW, no SPI interface - designed as companion chip to HMC960LP4E in cascaded baseband chains | Used upstream of HMC960LP4E for coarse gain; lacks dual-channel matching and common-mode control | Select when needing pre-VGA gain staging before HMC960LP4E - not a functional replacement |
| ADL5330ACPZ-R7 | Analog Devices dual VGA, 0–30 dB, 900 MHz BW, 50 Ω input/output, no programmable input impedance or independent CM control | Targeted at IF frequencies (up to 900 MHz); higher bandwidth but lower baseband precision and balance | Select for wider IF gain control; avoid for baseband I/Q where phase matching and CM flexibility are required |
Compared with HMC900LP5E and ADL5330ACPZ-R7, the HMC960LP4E uniquely combines dual-channel matching, programmable input impedance, independent common-mode control, and 0.5 dB gain resolution - making it irreplaceable for precision baseband I/Q signal chains demanding >55 dB sideband rejection.
Availability
HMC960LP4E is available at Aetrix Electronics and suitable for baseband ADC driver, direct-conversion transceiver, diversity receiver, and adaptive gain control applications requiring stable component supply and long-term production continuity.
Supply support for HMC960LP4E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global semiconductor leader specializing in high-performance analog, mixed-signal, and digital signal processing technologies for precision instrumentation, communications, and industrial systems.
The HMC960LP4E belongs to Analog Devices' High Frequency division RF & Microwave product line, engineered specifically for high-fidelity I/Q baseband signal conditioning in wireless infrastructure and test equipment.
FAQ
What is the maximum operating frequency and bandwidth specification for the HMC960LP4E?
The HMC960LP4E supports DC to 100 MHz signal bandwidth (3 dB point) across its full 0–40 dB gain range. Its 0.5 dB bandwidth exceeds 50 MHz, and it maintains excellent I/Q channel balance up to 100 MHz - verified in datasheet Figures 5 and 6. This makes the HMC960LP4E suitable for wideband baseband applications including LTE, WiMAX, and broadband test equipment where flat group delay and minimal phase distortion are essential. The HMC960LP4E does not operate at RF or IF frequencies above 100 MHz.
Does the HMC960LP4E support both SPI and parallel gain control simultaneously?
No - the HMC960LP4E uses register bit [5] in Settings Register (Reg 02h) to select the active gain source: '0' enables parallel port (GC[6:0]), '1' enables SPI-controlled gain from Register 03h. Both interfaces cannot be active concurrently. When SPI is selected, the GC pins are ignored; when parallel is selected, SPI writes to Reg 03h have no effect on gain. The HMC960LP4E must be configured at startup or runtime via this register to avoid undefined behavior.
What input impedance options does the HMC960LP4E provide, and how are they configured?
The HMC960LP4E offers two differential input impedance options: 100 Ω and 400 Ω. Configuration is performed via bit [4] (Rin_50ohm_select) in Settings Register (Reg 02h): '0' selects 200 Ω per side (400 Ω differential), '1' selects 50 Ω per side (100 Ω differential). This setting applies identically to both I and Q channels and persists across power cycles. The HMC960LP4E does not support dynamic reconfiguration of input impedance during operation - it is a static setup parameter.
How does the HMC960LP4E achieve its specified 0.5 dB gain step accuracy?
The HMC960LP4E achieves ±0.2 dB gain step accuracy (typical) through a resistor-ratio-based second gain stage, where gain increments are determined by precisely trimmed on-chip resistors rather than switched transistor arrays. This architecture minimizes temperature and process variation effects. Combined with gain decoding logic that optimally allocates gain across three internal stages, the HMC960LP4E maintains ±0.05 dB typical step error and ±0.2 dB absolute gain error at 40 MHz - as validated in Table 1 and Figures 2 and 4 of the datasheet.
Can the HMC960LP4E drive ADCs directly without external components?
Yes - the HMC960LP4E is designed as a direct ADC driver. Its differential outputs deliver up to 2 Vppd into 400 Ω loads and 1 Vppd into 100 Ω loads, matching common ADC input requirements. With externally set common-mode voltages (via CMI/CMQ pins) and programmable input impedance, the HMC960LP4E eliminates need for AC-coupling capacitors, level-shifters, or termination resistors in most implementations. The datasheet confirms successful interfacing with the HMCAD1520 ADC without additional circuitry.
131191-HMC960LP4E Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Packaging:
- Bag
- Product Status:
- Obsolete
- Type:
- Variable Gain Amplifier
- Frequency:
- 0Hz ~ 100MHz
- Contents:
- Board(s), Cable(s)
- Utilized IC / Part:
- HMC960LP4E
131191-HMC960LP4E FAQ
1.How can I place an order for 131191-HMC960LP4E through Aetrix?
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7.What is the process for return or replacement of 131191-HMC960LP4E?
All 131191-HMC960LP4E units undergo pre-shipment inspection (PSI). If there is an issue with 131191-HMC960LP4E, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 131191-HMC960LP4E part is unused and in its original packaging.
Return procedure for 131191-HMC960LP4E:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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