Texas Instruments 201-000795
- Part No.:
- 201-000795
- Manufacturer:
- Texas Instruments
- Category:
- Analog to Digital Converters (ADC)
- Package:
- -
- Datasheet:
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201-000795.pdf
- Description:
- IC ADC
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Product details
Overview
DDC232 from Texas Instruments is a 20-bit, 32-channel, current-input analog-to-digital converter with dual-switched integrator front-end architecture, ±0.025% integral linearity, 5.3ppm FSR noise, and 3.1 kSPS data rate in C-grade configuration. It directly digitizes photodiode currents without external I/V conversion and operates in CT scanner detector acquisition systems.
For engineers reviewing the DDC232 datasheet, DDC232 pinout, DDC232 application, or DDC232 equivalent, key selection criteria include full-scale range adjustability (12.5–350 pC), integration time programmability (166–1000 ms), daisy-chainable serial interface timing, and BGA-64 package thermal and layout constraints.
Technical Context
The DDC232 implements continuous-time dual-switched integration per channel: while one integrator side (A or B) integrates input current, the other is digitized by an onboard delta-sigma A/D converter. Each of the 32 inputs features matched integrators with on-chip trimmed capacitors (3–87.5 pF) selectable via 3-bit range control.
Its serial interface uses independent clocks-CLK for system timing and CONV for integration control-with DCLK for data output synchronization. The device supports two operating modes: continuous (integration time ≥ A/D conversion time) and noncontinuous (integration halted during digitization), determined by tINT and CLK frequency.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 20-bit output word with 19-bit no-missing-codes guarantee; enables sub-femtoampere current resolution at 350 pC full-scale. |
| Integral Linearity Error | ±0.025% of reading ±1.0 ppm of FSR (typical); ensures high-accuracy multi-channel charge accumulation without calibration per channel. |
| Input Noise | 5.3 ppm of FSR rms (at CSENSOR = 50 pF, Range 7); corresponds to ~1.68 fC rms noise floor for low-light photodiode signal fidelity. |
| Data Rate | 3.125 kSPS (DDC232C); defines maximum sustained sampling throughput across all 32 channels in continuous mode. |
| Integration Time | Adjustable from 160 ms to 1 s; determines minimum detectable current (fA–mA range) and anti-aliasing bandwidth (0.001–0.006 Hz). |
| Power Dissipation | 224 mW total (7 mW/channel); enables dense multi-DDC232 arrays in thermally constrained medical detector modules. |
| Analog Supply | +4.75 V to +5.25 V AVDD; powers integrators and reference circuitry with <±0.5 ppm/°C offset drift over 0–70°C. |
Pinout & Package
The DDC232 is housed in a 64-pin BGA package (10 mm × 10 mm, 0.8 mm pitch) with separate analog/digital ground planes and dedicated quiet analog ground (QGND) for integrator stability.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1–IN32 | Analog Input | 32 single-ended current-input terminals; each connects directly to photodiode cathodes without external transimpedance amplifiers. |
| CONV | Digital Input | Edge-triggered control signal toggling integration between side A and side B; must be synchronized to CLK rising edge within ±10 ns. |
| DVALID | Digital Output | Active-low strobe indicating valid 20-bit data in shift register; used to gate DCLK-driven readout in synchronous systems. |
| VREF | Analog Input | +4.096 V external reference input; resets integrator capacitors and sets full-scale range; requires low-noise buffered source per Figure 6. |
| AGND / DGND / QGND | Ground Terminal | Separate analog (AGND), digital (DGND), and quiet analog (QGND) pins prevent coupling between sensitive integrator nodes and switching logic. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-switched integrator per channel | Enables uninterrupted current integration: one side integrates while the other undergoes digitization, eliminating dead time in CT/X-ray pulse sequences. |
| On-chip adjustable full-scale range | Eight programmable ranges (12.5–350 pC) via 3-bit register; eliminates external gain-switching components and maintains channel-to-channel match ≤0.5% FSR. |
| Daisy-chainable serial interface | Single DIN-to-DOUT cascade path with common CLK/DCLK; reduces FPGA I/O count and PCB routing complexity in multi-sensor detector arrays. |
| In-package bypass capacitance | Integrated 0.1 µF decoupling caps per AVDD/DVDD pin; simplifies layout by removing discrete ceramic capacitors near BGA pads. |
| Low-power per-channel operation | 7 mW/channel (DDC232C); allows 32-channel digitization within 224 mW total, critical for air-cooled CT detector modules. |
Applications
| CT Scanner Detector Acquisition System | High-Dynamic-Range Photodiode Array Digitizer |
|---|---|
|
Use Scenario: Digitizing scintillation light pulses from 32 parallel photodiode rows in rotating gantry CT detectors. IC Role / Device Role / Timing Role: Current-input ADC performing continuous integration and synchronized conversion under precise CONV/CLK timing to capture microsecond-scale X-ray pulses. Use Value: 3.1 kSPS sustained rate and 5.3 ppm noise enable sub-millimeter spatial resolution and low-contrast object detection in clinical imaging. |
Use Scenario: Reading low-current outputs from large-area silicon photodiodes in radiation monitoring equipment. IC Role / Device Role / Timing Role: Direct current-to-digital conversion with programmable integration time (166–1000 ms) to adapt to varying photon flux levels. Use Value: Adjustable full-scale range (12.5–350 pC) and ±0.025% linearity eliminate per-sensor calibration, reducing field maintenance cost. |
| X-Ray Flat Panel Detector Front-End | Multi-Channel Ionization Chamber Readout |
|
Use Scenario: Converting ion current from amorphous selenium X-ray sensors into digital values for real-time image reconstruction. IC Role / Device Role / Timing Role: 32-channel simultaneous integration with dual integrator architecture ensuring zero dead time between exposure frames. Use Value: Dual-side integrator matching (≤0.5% FSR range error) preserves pixel-to-pixel uniformity across entire detector panel. |
Use Scenario: Measuring ultra-low ion currents (fA–pA) from environmental radiation chambers with temperature-stable accuracy. IC Role / Device Role / Timing Role: Precision integrating ADC with <±0.5 ppm/°C offset drift and integrated reference buffering support for long-term stability. Use Value: 0.1 ppm/°C range drift match between integrator sides enables drift-compensated differential measurement without external hardware. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar current-input ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TI DDC316 | 16-channel, 12 pC full-scale, 100 kSPS, 28 mW/channel, same BGA-64 package | Higher speed, lower resolution, narrower dynamic range; suited for fast transient detection rather than precision low-current integration | Select DDC316 when system requires >10× faster sampling and can accept reduced charge resolution and higher noise floor. |
| Analog Devices ADAS1000-3 | 5-channel, 24-bit, ECG-optimized, integrated lead-off detection, SPI interface, LFCSP-56 package | Medical-grade biopotential front-end with safety isolation; lacks current-input architecture and multi-channel density | Select ADAS1000-3 only for patient-connected biosignal acquisition where regulatory compliance and galvanic isolation are mandatory. |
Compared with DDC232, DDC316 trades channel count and integration depth for speed and power efficiency, while ADAS1000-3 targets isolated biopotential sensing-not direct photodiode current digitization-making neither a drop-in replacement but a functional alternative for distinct system-level requirements.
Availability
DDC232 is available at Aetrix Electronics and suitable for CT scanner detector modules, X-ray flat panel readout systems, high-resolution photodiode sensor arrays, and radiation dosimetry instrumentation requiring stable component supply across multi-year production cycles.
Supply support for DDC232 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-reliability ICs for industrial, medical, and automotive applications.
The DDC232 belongs to TI's precision current-input ADC product line, designed specifically for direct digitization of low-level photodiode and ion chamber currents in medical imaging and scientific instrumentation.
FAQ
What is the maximum integration time supported by the DDC232?
The DDC232 supports integration times from 160 ms to 1,000,000 ms (1 second) in continuous mode. This range is set by the combination of system clock (CLK) frequency and CONV timing, with longer durations enabling lower-noise measurements of ultra-low photocurrents. The DDC232 datasheet specifies tINT = 1,000,000 ms as the upper limit for continuous operation, and this value is confirmed for the DDC232 part number across all operating conditions.
Does the DDC232 require external integration capacitors?
No, the DDC232 does not require external integration capacitors. It integrates eight factory-trimmed capacitor values (3–87.5 pF) on-die for each of the 32 input channels, selected via the 3-bit Range[2:0] configuration register. External capacitors would disrupt the calibrated full-scale range and invalidate the specified linearity and noise performance of the DDC232.
How is daisy-chaining implemented on the DDC232?
Daisy-chaining on the DDC232 uses the DIN and DOUT pins: DOUT of one device connects to DIN of the next, while CLK, DCLK, CONV, and RESET are shared across all devices. Data is shifted out sequentially with each device contributing its 20-bit word, minimizing FPGA I/O usage. This topology is explicitly defined for the DDC232 in the SBAS331D datasheet and verified in TI reference designs.
What is the role of the QGND pin on the DDC232?
The QGND (Quiet Analog Ground) pin at H5 provides a dedicated low-noise return path for the most sensitive analog circuitry-including integrator op-amps and reference buffers-to isolate them from digital switching noise. Unlike AGND pins, QGND must be routed with minimal impedance to the system analog ground plane and not shared with any digital return paths. This requirement is specified in the DDC232 pin description table and layout guidelines.
Can the DDC232 operate with a 2.5V digital supply?
No, the DDC232 requires DVDD between +2.7 V and +3.6 V per its Absolute Maximum Ratings and Electrical Characteristics tables. Operation at 2.5 V violates the minimum DVDD specification and risks incorrect logic level interpretation, failed configuration register writes, and unstable DVALID/DOUT signaling. The DDC232 datasheet confirms +2.7 V as the absolute minimum for guaranteed functionality.
201-000795 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- *
- Package/Case:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Number of Bits:
- -
- Sampling Rate (Per Second):
- -
- Number of Inputs:
- -
- Input Type:
- -
- Data Interface:
- -
- Configuration:
- -
- Ratio - S/H:ADC:
- -
- Number of A/D Converters:
- -
- Architecture:
- -
- Reference Type:
- -
- Voltage - Supply, Analog:
- -
- Voltage - Supply, Digital:
- -
- Features:
- -
- Operating Temperature:
- -
- Supplier Device Package:
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- Mounting Type:
- -
- Grade:
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- Qualification:
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1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 201-000795 part is unused and in its original packaging.
Return procedure for 201-000795:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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