Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Memory > Memory

Microchip Technology 23AA04M-I/ST

Name: 23AA04M-I/ST
Brand: Microchip Technology
SKU: 23AA04M-I/ST
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: 23AA04M-I/ST

Manufacturer:: Microchip Technology

Category:: Memory

Package:: 8-TSSOP (0.173", 4.40mm Width)

Datasheet:: 23AA04M-I/ST.pdf

Description:: IC SRAM 4MBIT SPI/QUAD 8TSSOP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,392

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

23AA04M-I/ST from Microchip Technology is a 4,096-Kbit serial SRAM with SPI/SDI/SQI interface, 1.7V–3.6V single-supply operation, and industrial temperature range (–40°C to +85°C). It delivers 143 MHz high-speed read capability in SQI mode, built-in ECC logic for data integrity, and supports byte/page/sequential access modes. Used in real-time data logging systems where nonvolatile backup is not required but fast, reliable volatile memory is critical.

For engineers reviewing the 23AA04M-I/ST datasheet, 23AA04M-I/ST pinout, 23AA04M-I/ST application, or 23AA04M-I/ST equivalent, key selection criteria include its 8-lead TSSOP package, absence of VBAT pin, SPI/SDI/SQI protocol flexibility, 143 MHz max clock frequency in SQI mode, and ECC-enabled reliability for mission-critical buffer applications.

Technical Context

The 23AA04M-I/ST implements a quad-capable serial interface supporting SPI (mode 0/3), SDI (2-bit I/O), and SQI (4-bit I/O) protocols - all configurable via command instructions (EDIO/EQIO/RSTIO). Its internal STATUS register controls page size (32/256 bytes), output drive strength (8 levels), slew rate (4 settings), and latches ECC correction events.

It operates exclusively in 8-lead packages (SOIC/PDIP/TSSOP) with no VBAT pin, distinguishing it from the 14-lead 23LCV04M. Power-up behavior requires CS low before any command; HOLD/SIO3 enables pause/resume of ongoing transfers without resetting the clock sequence.

Key Specifications

Parameter	Value and Actual Design Meaning
Memory Size	4,096 Kbit (512 KB), organized as 256 × 8-bit pages with user-selectable 32- or 256-byte page size
Interface Modes	SPI (mode 0/3), SDI (2-line multiplexed), SQI (4-line multiplexed); configured dynamically via EDIO/EQIO commands
Max Clock Frequency	143 MHz in SQI mode; 40 MHz in SPI/SDI read (0x03); enables up to 572 MB/s effective throughput in quad mode
Voltage Range	1.7V–3.6V supply; supports direct integration with 1.8V/2.5V/3.3V logic domains without level shifters
ECC Support	Built-in Error Correction Code logic detects and corrects single-bit errors per read cycle; ECS bit in STATUS register flags correction event
Power Consumption	6 mA max active current @ 40 MHz/3.6V; 140 µA typical standby current @ 25°C; enables low-power edge buffering
Temperature Range	Industrial grade: –40°C to +85°C; qualified for deployment in automotive infotainment control units and industrial PLCs

Pinout & Package

23AA04M-I/ST is supplied in an 8-lead TSSOP package (ST suffix), pin-compatible with 8-lead SOIC and PDIP variants. No VBAT pin is present - battery backup is not supported.

Pin/Terminal	Circuit Role	Design Meaning
1: CS	Chip Select Input	Active-low enable; forces SO to high-Z when deasserted, enabling multi-device SPI bus sharing
2: SO/SIO1	Serial Output / SDI/SQI I/O	Outputs data in SPI mode; bidirectional in SDI/SQI; driven after SCK falling edge
3: SIO2	SQI Quad I/O Pin	Active only in SQI mode; bidirectional data line; doubles bandwidth vs SDI, quadruples vs SPI
4: VSS	Ground Reference	Primary return path for all digital and I/O circuits; must be low-impedance connection
5: SI/SIO0	Serial Input / SDI/SQI I/O	Latches data on SCK rising edge in SPI; bidirectional in SDI/SQI; shares pin with SO in dual/quad modes
6: SCK	Serial Clock Input	Synchronizes all data transfers; supports mode 0 (SCK low idle) and mode 3 (SCK high idle)
7: HOLD/SIO3	HOLD Control / SQI I/O	Pauses ongoing transfers in SPI/SDI mode; functions as fourth I/O in SQI; tri-states SO immediately on low assertion
8: VCC	Power Supply	1.7V–3.6V input; powers core logic, I/O buffers, and ECC circuitry; no internal regulation

Key Features

Feature	Design Value
Triple-Mode Serial Interface	Hardware-configurable SPI/SDI/SQI operation via command set - eliminates need for external mode-select logic or PCB redesign
143 MHz SQI Read Throughput	Enables 572 MB/s peak data rate using 4-bit I/O, reducing host CPU overhead in high-bandwidth sensor fusion applications
User-Selectable Page Size	32-byte or 256-byte pages controlled by STATUS register bit 8 - optimizes write efficiency for small packet logging or large firmware patching
On-Chip ECC Logic	Detects and corrects single-bit errors per read; ECS bit provides observable fault indicator for system-level error reporting and diagnostics
Configurable Output Drive & Slew	8 drive strength levels (12.5%–100%) and 4 slew rates (1.44–6.00 V/ns) allow signal integrity tuning across varied trace lengths and loads

Applications

Industrial Data Logger	Medical Sensor Hub
Use Scenario: Continuous acquisition of vibration, temperature, and pressure data from factory-floor machinery at 10 kHz sample rate, buffered before SD card write. IC Role / Device Role / Timing Role: High-speed volatile buffer providing zero-write-time storage with ECC-protected integrity during burst reads by ARM Cortex-M7 host. Use Value: 143 MHz SQI interface sustains 572 MB/s read bursts; 32-byte page mode minimizes write latency for timestamped 16-bit samples; ECC prevents silent corruption in long-duration logging.	Use Scenario: Aggregation of ECG, SpO₂, and respiration signals from multiple analog front-ends into a central microcontroller for real-time analysis and alarm triggering. IC Role / Device Role / Timing Role: Low-latency, low-power SRAM buffer decoupling ADC sampling from processing - operating at 1.8V supply with 140 µA standby current between acquisitions. Use Value: 1.7V minimum VCC enables direct connection to 1.8V medical SoC rails; configurable slew rate suppresses EMI in sensitive analog zones; industrial temp rating ensures reliability in clinical environments.
Automotive Infotainment UI Cache	Industrial PLC Configuration Store
Use Scenario: Caching of GUI assets (icons, fonts, menu trees) in head-unit display subsystem to reduce boot time and improve touch response. IC Role / Device Role / Timing Role: Fast-access serial memory serving as L2 cache between application processor and display controller, accessed via 143 MHz SQI bus. Use Value: 256-byte page mode accelerates loading of compressed bitmap tiles; HOLD pin allows seamless interruption during CAN bus interrupt servicing without data loss or reinitialization.	Use Scenario: Storing runtime configuration parameters, calibration tables, and I/O mapping data in programmable logic controllers deployed in harsh manufacturing environments. IC Role / Device Role / Timing Role: Industrial-grade serial RAM retaining volatile state during brief brownouts; accessed via SPI from Cortex-M4F real-time core. Use Value: –40°C to +85°C rating ensures operation inside sealed control cabinets; ECC protects against cosmic-ray-induced bit flips in long-life deployments; unlimited write cycles eliminate wear-out concerns.

Industrial Data Logger

Medical Sensor Hub

Use Scenario: Continuous acquisition of vibration, temperature, and pressure data from factory-floor machinery at 10 kHz sample rate, buffered before SD card write.

IC Role / Device Role / Timing Role: High-speed volatile buffer providing zero-write-time storage with ECC-protected integrity during burst reads by ARM Cortex-M7 host.

Use Value: 143 MHz SQI interface sustains 572 MB/s read bursts; 32-byte page mode minimizes write latency for timestamped 16-bit samples; ECC prevents silent corruption in long-duration logging.

Use Scenario: Aggregation of ECG, SpO₂, and respiration signals from multiple analog front-ends into a central microcontroller for real-time analysis and alarm triggering.

IC Role / Device Role / Timing Role: Low-latency, low-power SRAM buffer decoupling ADC sampling from processing - operating at 1.8V supply with 140 µA standby current between acquisitions.

Use Value: 1.7V minimum VCC enables direct connection to 1.8V medical SoC rails; configurable slew rate suppresses EMI in sensitive analog zones; industrial temp rating ensures reliability in clinical environments.

Automotive Infotainment UI Cache

Industrial PLC Configuration Store

Use Scenario: Caching of GUI assets (icons, fonts, menu trees) in head-unit display subsystem to reduce boot time and improve touch response.

IC Role / Device Role / Timing Role: Fast-access serial memory serving as L2 cache between application processor and display controller, accessed via 143 MHz SQI bus.

Use Value: 256-byte page mode accelerates loading of compressed bitmap tiles; HOLD pin allows seamless interruption during CAN bus interrupt servicing without data loss or reinitialization.

Use Scenario: Storing runtime configuration parameters, calibration tables, and I/O mapping data in programmable logic controllers deployed in harsh manufacturing environments.

IC Role / Device Role / Timing Role: Industrial-grade serial RAM retaining volatile state during brief brownouts; accessed via SPI from Cortex-M4F real-time core.

Use Value: –40°C to +85°C rating ensures operation inside sealed control cabinets; ECC protects against cosmic-ray-induced bit flips in long-life deployments; unlimited write cycles eliminate wear-out concerns.

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial SRAM applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
23LCV04M-I/ST	14-lead TSSOP with VBAT pin; 2.2V–3.6V VCC range; supports external battery backup for data retention during power loss	Required where nonvolatile data hold during main supply interruption is mandatory (e.g., energy metering, safety-critical state save)	Select 23LCV04M-I/ST only if VBAT functionality is needed; incompatible pinout prevents drop-in replacement
IS66WV25616EALL-100BLI	Parallel-interface 256K × 16-bit SRAM in 48-pin TSOP; 3.3V-only; no ECC; 100 MHz async access; no serial protocol support	Suitable for legacy designs with parallel bus architecture and no space for serial-to-parallel bridge logic	Choose IS66WV25616EALL-100BLI only when existing PCB layout mandates parallel interface; higher pin count and power draw versus 23AA04M-I/ST

Compared with 23LCV04M-I/ST, the 23AA04M-I/ST omits VBAT and uses an 8-lead footprint - simplifying layout and lowering BOM cost where backup is unnecessary. Versus IS66WV25616EALL-100BLI, it reduces pin count by >80% and adds protocol flexibility and ECC, at the cost of requiring SPI/SQI host support.

Availability

23AA04M-I/ST is available at Aetrix Electronics and suitable for industrial data loggers, medical sensor hubs, automotive infotainment UI caches, and industrial PLC configuration stores requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.

Supply support for 23AA04M-I/ST includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology Inc. is a leading provider of microcontrollers, analog components, and memory solutions, headquartered in Chandler, Arizona, with global design and manufacturing operations.

The 23AA04M-I/ST belongs to Microchip's 23XX04M serial SRAM product line, engineered for high-speed, low-voltage, protocol-flexible volatile memory in space-constrained embedded systems where ECC-enhanced reliability is essential.

FAQ

Does the 23AA04M-I/ST support battery backup for data retention?

No, the 23AA04M-I/ST does not support battery backup. It lacks the VBAT pin present on the 23LCV04M variant. Data retention relies solely on continuous VCC supply within the 1.7V–3.6V range. For applications requiring data hold during power loss, the 23LCV04M-I/ST is the appropriate alternative with automatic VCC-to-VBAT switchover at 1.75–1.95V threshold.

What is the maximum clock frequency supported by the 23AA04M-I/ST in each interface mode?

The 23AA04M-I/ST supports up to 143 MHz in SQI mode for both read and write operations. In SPI and SDI modes, the READ instruction (0x03) is limited to 40 MHz, while the HIGH-SPEED READ instruction (0x0B) operates at 143 MHz. Write operations using 0x02 command run at 143 MHz across all modes, as confirmed in Table 3-1 of the datasheet.

How does the built-in ECC logic function in the 23AA04M-I/ST?

The 23AA04M-I/ST implements on-chip ECC that automatically detects and corrects single-bit errors during every read operation. The Error Correction State (ECS) bit in the STATUS register (bit 13) is set to '1' when correction is applied, providing a hardware-flagged diagnostic signal. ECC operates transparently - no software intervention or additional timing overhead is required beyond reading the STATUS register post-read.

Can the 23AA04M-I/ST be used in a 3.3V-only system without level shifting?

Yes, the 23AA04M-I/ST is fully compatible with 3.3V systems. Its VCC range (1.7V–3.6V) and input thresholds (VIH = 0.7×VCC, VIL = 0.3×VCC) ensure robust interfacing with standard 3.3V CMOS logic. At VCC = 3.3V, VIH is 2.31V min and VIL is 0.99V max - well within 3.3V logic margins. No external level shifters are needed for host MCU GPIOs.

What package type does the 23AA04M-I/ST use, and is it pin-compatible with other variants?

The 23AA04M-I/ST uses an 8-lead TSSOP package (ST suffix), identical in footprint and pinout to the 8-lead SOIC (SN) and PDIP (P) versions. It is not pin-compatible with the 14-lead 23LCV04M-I/ST due to differing pin count, VBAT inclusion, and NC pin placement. Always verify land pattern against Microchip's 8-lead TSSOP mechanical drawing.

23AA04M-I/ST Specifications

Product attributes: Attribute value

Manufacturer:: Microchip Technology

Series:: -

Package/Case:: 8-TSSOP (0.173", 4.40mm Width)

Packaging:: Tube

Product Status:: Active

Programmable:: -

Memory Type:: Volatile

Memory Format:: SRAM

Technology:: SRAM - Synchronous

Memory Size:: 4Mbit

Memory Organization:: 512K x 8

Memory Interface:: SPI - Quad I/O

Clock Frequency:: 143 MHz

Write Cycle Time - Word, Page:: -

Access Time:: 7 ns

Voltage - Supply:: 1.7V ~ 3.6V

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 8-TSSOP

23AA04M-I/ST FAQ

1.How can I place an order for 23AA04M-I/ST through Aetrix?

Please submit a Request for Quotation (RFQ) for 23AA04M-I/ST on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 23AA04M-I/ST reliable?

The price and inventory of 23AA04M-I/ST are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 23AA04M-I/ST is usually 5 days.

3.What payment methods are accepted for 23AA04M-I/ST?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 23AA04M-I/ST transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 23AA04M-I/ST?

23AA04M-I/ST orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 23AA04M-I/ST order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 23AA04M-I/ST?

For technical support, including 23AA04M-I/ST datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 23AA04M-I/ST requirements.

6.How does Aetrix verify that 23AA04M-I/ST is sourced from the original manufacturer or authorized distributors?

All 23AA04M-I/ST products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 23AA04M-I/ST meets industry standards.

7.What is the process for return or replacement of 23AA04M-I/ST?

All 23AA04M-I/ST units undergo pre-shipment inspection (PSI). If there is an issue with 23AA04M-I/ST, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 23AA04M-I/ST part is unused and in its original packaging.

Return procedure for 23AA04M-I/ST:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…