Microchip Technology 24AA04H-I/ST

Overview

24AA04H-I/ST from Microchip Technology Inc. is a 4-Kbit I²C-compatible serial EEPROM organized as two 256 × 8-bit blocks, operating from 1.7V to 5.5V with 400 kHz max clock frequency (100 kHz below 2.5V), 1 µA standby current, and hardware write-protect for half-array (100h–1FFh). It supports industrial temperature range (−40°C to +85°C) and is used in embedded system configuration storage where low-voltage operation and data retention >200 years are critical.

For engineers reviewing the 24AA04H-I/ST datasheet, 24AA04H-I/ST pinout, 24AA04H-I/ST application, or 24AA04H-I/ST equivalent, key selection criteria include I²C timing compliance at 1.7V, page write buffer size (16 bytes), half-array write-protection behavior, endurance (1 million cycles), and ST-package thermal and mounting characteristics.

Technical Context

The 24AA04H-I/ST implements a two-wire I²C interface with Schmitt-trigger inputs and slope-controlled outputs to suppress noise and eliminate ground bounce. Its internal address counter enables current-address, random, and sequential read modes, while ACK polling supports bus efficiency during write-cycle completion detection.

It uses a 16-byte page write buffer with self-timed erase/write cycles (≤5 ms), and hardware write-protection is controlled via the WP pin: tied to VCC disables writes to addresses 100h–1FFh only, leaving 000h–0FFh fully writable. Pins A0–A2 are unconnected and may be left floating or tied to VSS/VCC.

Key Specifications

Pinout & Package

24AA04H-I/ST is supplied in an 8-lead SOIC package (SN), 3.90 mm body width, with standard gull-wing leads and JEDEC-compliant footprint. Pin 1 is marked by a beveled corner or notch.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial EEPROM applications.

Compared with 24LC04BH-I/ST, the 24AA04H-I/ST enables true 1.7V operation in ultra-low-power systems, while AT24C04-PU trades hardware protection for broader vendor availability but demands firmware-level data integrity safeguards.

Availability

24AA04H-I/ST is available at Aetrix Electronics and suitable for smart metering, industrial PLCs, automotive body control modules, and medical device logging requiring stable component supply, long-lifecycle support, and RoHS-compliant packaging.

Supply support for 24AA04H-I/ST includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology Inc. is a leading provider of microcontrollers, analog devices, and memory solutions, headquartered in Chandler, Arizona, with global design and manufacturing operations.

The 24AA04H-I/ST belongs to Microchip's 24XX04H family of serial EEPROMs, designed specifically for space-constrained, low-power embedded systems needing reliable nonvolatile storage with I²C simplicity and industrial-grade robustness.

FAQ

What is the maximum clock frequency supported by the 24AA04H-I/ST?

The 24AA04H-I/ST supports up to 400 kHz when VCC is 2.5V or higher. At VCC between 1.7V and 2.49V, the maximum clock frequency is reduced to 100 kHz to ensure reliable I²C timing margins. This dual-speed capability allows seamless integration across 1.8V, 3.3V, and 5V platforms without protocol changes. The 24AA04H-I/ST datasheet specifies these limits in Table 1-2 under AC Characteristics.

Does the 24AA04H-I/ST require external pull-up resistors on SDA and SCL lines?

Yes, the 24AA04H-I/ST requires external pull-up resistors on both SDA and SCL lines because its I²C interface uses open-drain outputs. Typical values are 10 kΩ for 100 kHz operation and 2 kΩ for 400 kHz. The exact value depends on bus capacitance and rise-time requirements. This is explicitly stated in Section 2.2 of the 24AA04H-I/ST datasheet under "Serial Address/Data Input/Output (SDA)".

How does the write-protect feature work on the 24AA04H-I/ST?

The 24AA04H-I/ST uses the WP pin to enable hardware write protection: when WP is tied to VCC, writes to memory addresses 100h–1FFh are inhibited while reads remain fully functional; addresses 000h–0FFh stay writable. When WP is tied to VSS, full-array write access is enabled. This half-array protection is implemented entirely within the 24AA04H-I/ST silicon and requires no firmware intervention.

What is the purpose of pins A0, A1, and A2 on the 24AA04H-I/ST?

Pins A0, A1, and A2 on the 24AA04H-I/ST are not internally connected and serve no functional role. They may be left floating or tied to VSS or VCC without affecting device operation. This is confirmed in Section 2.1 ("A0, A1, A2") and Table 2-1 of the 24AA04H-I/ST datasheet, which lists them as "Not Connected" for all package variants including the ST (SOIC) package.

Is the 24AA04H-I/ST compatible with standard I²C protocols and controllers?

Yes, the 24AA04H-I/ST is fully compliant with the standard two-wire I²C bus protocol, supporting Start/Stop conditions, ACK/NACK signaling, and 7-bit addressing with fixed '1010' control code. It interoperates with any I²C master (e.g., STM32, PIC, ESP32) without custom drivers. Protocol details-including current-address, random, and sequential read modes-are defined in Sections 3.0–8.0 of the 24AA04H-I/ST datasheet.