Microchip Technology 24AA128-I/SNG
- Part No.:
- 24AA128-I/SNG
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
24AA128-I/SNG.pdf
- Description:
- IC EEPROM 128KBIT I2C 8SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
24AA128-I/SNG from Microchip Technology is a 128 Kbit (16K × 8) I²C-compatible serial EEPROM with 1.7V–5.5V single-supply operation, 400 kHz maximum clock frequency, and industrial temperature range (−40°C to +85°C). It features 64-byte page write buffer, hardware write-protect (WP), Schmitt-trigger inputs, and >1 million erase/write cycles - deployed in embedded system configuration storage, sensor calibration data retention, and power-fail-safe parameter backup.
For engineers reviewing the 24AA128-I/SNG datasheet, 24AA128-I/SNG pinout, 24AA128-I/SNG application, or 24AA128-I/SNG equivalent, this page delivers verified electrical specs, package mapping to SOIC-8 (SNG), I²C timing compliance at 1.7V–5.5V, WP-controlled write protection behavior, and real-world use context for industrial-grade nonvolatile memory selection.
Technical Context
The 24AA128-I/SNG implements a two-wire I²C slave interface with fixed 4-bit control code (1010b) and user-configurable A2/A1/A0 address bits enabling up to eight devices on one bus. Its internal architecture includes a 64-byte page latch, HV generator for EEPROM programming, and address pointer logic supporting current-address, random, and sequential reads across the full 0000h–3FFFh address space.
Write operations are self-timed with ≤5 ms byte/page cycle duration; acknowledge polling is supported during write cycles. The device samples WP at the Stop bit to enable/disable writes, and uses open-drain SDA/SCL with internal Schmitt triggers and slope control to suppress noise and ground bounce - critical for noisy industrial PCB environments.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 128 Kbit (16,384 × 8), organized as 2048 pages of 64 bytes - enables efficient bulk parameter storage without external addressing logic. |
| Supply Voltage Range | 1.7V to 5.5V - supports direct interfacing with 1.8V, 2.5V, 3.3V, and 5V microcontrollers without level shifters. |
| I²C Clock Frequency | Up to 400 kHz (100 kHz below 2.5V) - ensures compatibility with standard-mode I²C masters while maintaining timing margin at low VCC. |
| Write Endurance | ≥1,000,000 cycles per page - guarantees long-term reliability in firmware update logging or runtime calibration storage. |
| Data Retention | ≥200 years at +85°C - validated for lifetime data integrity in unattended industrial equipment. |
| Standby Current | ≤1 µA at VCC = 5.5V, I-temp - minimizes quiescent power in battery-backed or energy-harvesting systems. |
| Page Write Time | ≤5 ms maximum - defines worst-case latency for saving configuration blocks; enables deterministic system response. |
Pinout & Package
24AA128-I/SNG is packaged in an 8-lead SOIC (Small Outline Integrated Circuit) with narrow body (3.90 mm), JEDEC MS-012 variant, marked "SNG" per Microchip's packaging nomenclature. Pin 1 is top-left corner with notch or dot marking; leads are gull-wing, matte tin-plated.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0 | Chip Address Input | User-configurable LSB of 3-bit slave address (1010xxxA); hardwired to VSS/VCC to select one of eight possible I²C addresses on shared bus. |
| A1 | Chip Address Input | Middle bit of slave address; determines device select when multiple 24AA128-I/SNG units share SDA/SCL lines. |
| A2 | Chip Address Input | MSB of slave address; enables contiguous 1 Mbit expansion across up to eight devices via software-managed A14–A16 mapping. |
| VSS | Ground Reference | Primary return path for all internal circuitry; must be low-impedance connection to system GND plane. |
| SDA | Serial Data I/O | Open-drain bidirectional bus line requiring external pull-up (2–10 kΩ); carries address, command, and data; changes only during SCL low. |
| SCL | Serial Clock Input | Master-generated clock synchronizing all I²C transfers; rising edge samples SDA, falling edge allows SDA transition. |
| WP | Hardware Write-Protect | Active-high input sampled at Stop bit: tied to VCC disables all writes (read-only mode), tied to VSS enables full read/write access. |
| VCC | Power Supply | Single supply input (1.7–5.5V); powers EEPROM array, logic, and I/O buffers; requires local 0.1 µF ceramic decoupling. |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger inputs on SDA/SCL | 50 ns spike suppression + 0.05×VCC hysteresis - eliminates false triggering from EMI or signal ringing in industrial enclosures. |
| Output slope control | Controlled rise/fall times (≤300 ns @ VCC ≥2.5V) - prevents ground bounce and crosstalk during I²C transitions. |
| 64-byte page write buffer | Reduces I²C transaction overhead by up to 64× vs. byte-write; enables atomic save of multi-parameter sets. |
| Factory programming support | Allows pre-loading of calibration constants, MAC addresses, or security keys before board assembly - reduces post-production test time. |
| RoHS-compliant & AEC-Q100 qualified | Meets automotive stress testing (temperature, humidity, vibration) - suitable for under-hood and infotainment subsystems. |
Applications
| Industrial Sensor Node | Medical Device Calibration |
|---|---|
Use Scenario: Storing factory-calibrated offset/gain coefficients and linearization tables for analog sensor front-ends in programmable logic controllers. IC Role / Device Role / Timing Role: Nonvolatile configuration register holding persistent sensor metadata; accessed during power-on initialization and field recalibration. Use Value: Eliminates need for external MCU flash partitioning; retains accuracy over 200-year lifetime despite thermal cycling in factory environments. |
Use Scenario: Securing patient-specific therapy parameters and usage logs in portable infusion pumps with battery backup. IC Role / Device Role / Timing Role: Fail-safe parameter vault; writes occur only during safe states (e.g., pause mode), protected by WP pin during active delivery. Use Value: Guarantees <1 µA standby draw to extend battery life; withstands >1M write cycles required for daily usage logging over 5+ years. |
| Smart Energy Meter | Automotive Body Control Module |
Use Scenario: Recording tamper events, tariff schedules, and metering history in ANSI C12.22-compliant electricity meters with 10-year deployment life. IC Role / Device Role / Timing Role: Secure event logger with WP-enforced write lock after commissioning; accessed via isolated I²C bus. Use Value: Meets IEC 62056-21 data integrity requirements; 1.7V operation ensures reliable writes during brown-out conditions. |
Use Scenario: Storing seat position presets, mirror angles, and lighting profiles in vehicle door modules with CAN/I²C gateway architecture. IC Role / Device Role / Timing Role: Configuration EEPROM interfaced to 3.3V MCU; WP tied to ignition-sensed voltage to prevent accidental overwrites. Use Value: AEC-Q100 qualification ensures operation at −40°C to +85°C under hood; 400 kHz speed enables fast profile recall during door unlock. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 24LC128-I/SN | Requires minimum 2.5V VCC; identical pinout, timing, and memory map - no layout change needed. | Not suitable for 1.8V systems; limited to 2.5–5.5V rails where higher voltage stability is guaranteed. | Select when operating exclusively above 2.5V and cost sensitivity outweighs low-voltage flexibility. |
| AT24C128-10PU-2.7 | Same 128 Kbit capacity, 1 MHz max clock, but requires 2.7–5.5V; different A0/A1/A2 default state handling. | Lacks 1.7V operation and AEC-Q100 qualification; endurance rated at 100K cycles (vs. 1M). | Choose for legacy Atmel-based designs where 1 MHz speed is prioritized over ultra-low-voltage operation. |
Compared with 24LC128-I/SN and AT24C128-10PU-2.7, the 24AA128-I/SNG uniquely supports 1.7V operation and automotive qualification while retaining full pin and functional compatibility with the 24XX128 family - making it the optimal choice for next-generation low-power industrial and automotive systems requiring extended voltage margin and long-term reliability.
Availability
24AA128-I/SNG is available at Aetrix Electronics and suitable for industrial sensor nodes, medical device calibration storage, smart energy metering, and automotive body control modules requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for 24AA128-I/SNG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontroller, mixed-signal, analog, and Flash-IP solutions, headquartered in Chandler, Arizona, with global design and manufacturing operations.
The 24AA128-I/SNG belongs to Microchip's 24XX serial EEPROM product line, engineered for robust, low-power nonvolatile data storage in resource-constrained embedded systems where reliability, voltage flexibility, and I²C interoperability are critical.
FAQ
What is the minimum operating voltage for the 24AA128-I/SNG?
The 24AA128-I/SNG operates down to 1.7V DC, enabling direct integration with 1.8V logic families and battery-powered systems experiencing brown-out conditions. This is confirmed in the Device Selection Table and Electrical Characteristics section of DS20001191T, where VCC min is explicitly specified as 1.7V for the 24AA128 variant.
Does the 24AA128-I/SNG support 1 MHz I²C communication?
No, the 24AA128-I/SNG supports up to 400 kHz I²C clock frequency (100 kHz below 2.5V). The 1 MHz capability applies only to the 24FC128 variant. This distinction is clearly stated in the Device Selection Table and AC Characteristics table (Param. No. 1, FCLK) of DS20001191T.
How does the WP pin function on the 24AA128-I/SNG?
The WP (Write-Protect) pin on the 24AA128-I/SNG is sampled at the Stop bit of each write command. When tied to VCC, it disables all write operations (including page and byte writes) while permitting unlimited reads. When tied to VSS, full read/write access is enabled - a hardware-level safeguard against accidental overwrites.
What package type does the 'SNG' suffix indicate for the 24AA128-I/SNG?
The 'SNG' suffix denotes an 8-lead SOIC (Small Outline Integrated Circuit) package with narrow body (3.90 mm), per Microchip's standardized packaging nomenclature. This matches the SN package designation in the Device Selection Table and is documented in Microchip Drawing No. C04-057-SN Rev E.
Can multiple 24AA128-I/SNG devices share the same I²C bus?
Yes - up to eight 24AA128-I/SNG devices can be cascaded on a single I²C bus using unique combinations of A0, A1, and A2 address pins. Each device responds only to its assigned 7-bit slave address (1010xxxA), enabling scalable memory expansion up to 1 Mbit without additional address decoding logic.
24AA128-I/SNG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 128Kbit
- Memory Organization:
- 16K x 8
- Memory Interface:
- I2C
- Clock Frequency:
- 400 kHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- 900 ns
- Voltage - Supply:
- 1.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
24AA128-I/SNG FAQ
1.How can I place an order for 24AA128-I/SNG through Aetrix?
Please submit a Request for Quotation (RFQ) for 24AA128-I/SNG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 24AA128-I/SNG reliable?
The price and inventory of 24AA128-I/SNG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 24AA128-I/SNG is usually 5 days.
3.What payment methods are accepted for 24AA128-I/SNG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 24AA128-I/SNG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 24AA128-I/SNG?
24AA128-I/SNG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 24AA128-I/SNG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 24AA128-I/SNG?
For technical support, including 24AA128-I/SNG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 24AA128-I/SNG requirements.
6.How does Aetrix verify that 24AA128-I/SNG is sourced from the original manufacturer or authorized distributors?
All 24AA128-I/SNG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 24AA128-I/SNG meets industry standards.
7.What is the process for return or replacement of 24AA128-I/SNG?
All 24AA128-I/SNG units undergo pre-shipment inspection (PSI). If there is an issue with 24AA128-I/SNG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 24AA128-I/SNG part is unused and in its original packaging.
Return procedure for 24AA128-I/SNG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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