Microchip Technology 24AA128-I/ST
- Part No.:
- 24AA128-I/ST
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
24AA128-I/ST.pdf
- Description:
- IC EEPROM 128KBIT I2C 8TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:231
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
24AA128-I/ST from Microchip Technology Inc. is a 128 Kbit (16K × 8) I²C-compatible serial EEPROM designed for nonvolatile data storage in low-power embedded systems. It operates from 1.7V to 5.5V, supports up to 400 kHz I²C clock frequency at industrial temperature (–40°C to +85°C), features hardware write-protection via the WP pin, and delivers 64-byte page write capability with ≤5 ms self-timed write cycle. It is used in firmware parameter storage for smart sensors and configuration retention in battery-powered IoT edge nodes.
For engineers reviewing the 24AA128-I/ST datasheet, 24AA128-I/ST pinout, 24AA128-I/ST application, or 24AA128-I/ST equivalent, key selection criteria include its 1.7V minimum supply voltage, industrial-grade temperature rating, SOIC-8 (ST) package compatibility, and support for cascaded multi-device I²C bus configurations up to eight units.
Technical Context
The 24AA128-I/ST implements a two-wire I²C interface with Schmitt-trigger inputs on SDA and SCL for noise immunity, slope-controlled outputs to suppress ground bounce, and internal address pointer logic enabling current-address, random, and sequential read modes. Its memory array is organized as 16,384 × 8 bits with 64-byte page boundaries.
Write protection is enforced by the WP pin sampled at the Stop bit of each write command; when tied to VCC, all array writes (0000h–3FFFh) are inhibited while reads remain fully functional. Addressing uses a 7-bit slave address (1010xxxR/W) where A2–A0 pins define device select bits, allowing up to eight devices on one bus (two for MSOP).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 128 Kbit (16,384 × 8) nonvolatile EEPROM array |
| VCC range | 1.7V to 5.5V - enables direct interfacing with 1.8V, 3.3V, and 5V microcontrollers without level shifters |
| I²C clock max | 400 kHz at VCC ≥ 2.5V - supports standard-mode I²C timing with 600 ns minimum SCL high time |
| Page write buffer | 64 bytes - allows efficient bulk writes without host-side byte-by-byte overhead |
| Write endurance | 1,000,000 erase/write cycles per page - ensures long-term reliability in frequent configuration update scenarios |
| Data retention | >200 years at +85°C - guarantees persistent storage integrity across product lifetime in industrial environments |
| Standby current | ≤1 µA at I-temp - minimizes quiescent power draw in always-on battery-backed applications |
Pinout & Package
24AA128-I/ST is supplied in an 8-lead SOIC package (JEDEC MS-012, body width 3.90 mm), marked "24AA128I" and "ST" per Microchip's marking convention. Pin 1 is top-left corner with notch or dot indicator.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0 | Chip address input | LSB of 3-bit hardware slave address; hardwired to VSS or VCC to configure I²C device address (1010xxx) |
| A1 | Chip address input | Middle bit of slave address; determines unique I²C address among up to eight devices on same bus |
| A2 | Chip address input | MSB of slave address; enables full 1 Mbit cascaded address space when combined across multiple devices |
| VSS | Ground reference | Return path for all internal circuitry and I/O; must be connected to system GND plane |
| SDA | Serial data I/O | Open-drain bidirectional line requiring external pull-up resistor (2–10 kΩ); carries address, data, and ACK/NACK |
| SCL | Serial clock input | Master-generated clock signal synchronizing all I²C transfers; Schmitt-triggered for noise rejection |
| WP | Hardware write-protect | Active-high enable: tied to VCC blocks all writes; tied to VSS permits full read/write access |
| VCC | Power supply | Primary supply rail (1.7–5.5V); powers EEPROM core, interface logic, and charge pump for write operations |
Key Features
| Feature | Design Value |
|---|---|
| Low-voltage operation | Functional down to 1.7V - supports direct integration with 1.8V logic families and energy-harvesting systems |
| Noise-immune interface | Schmitt-trigger inputs + output slope control - eliminates false Start/Stop detection and ground bounce in noisy industrial PCBs |
| Page write efficiency | 64-byte buffer with ≤5 ms write cycle - reduces host CPU intervention and bus occupancy during firmware updates |
| Endurance assurance | 1M write cycles per page with >200-year data retention - validated for mission-critical configuration storage in unattended equipment |
| Hardware security | Dedicated WP pin sampled at Stop bit - prevents accidental or malicious overwrites without software involvement |
Applications
| Smart Sensor Calibration Storage | Industrial PLC Configuration Backup |
|---|---|
Use Scenario: Storing factory-calibrated sensor offset/gain coefficients and temperature compensation tables in MEMS pressure sensors. IC Role / Device Role / Timing Role: Nonvolatile configuration register holding critical calibration data accessed at power-up before ADC initialization. Use Value: Enables plug-and-play sensor replacement without field recalibration; leverages 1.7V operation for compatibility with ultra-low-power sensor front-ends. |
Use Scenario: Retaining user-defined I/O mapping, PID tuning parameters, and alarm thresholds in DIN-rail mounted programmable logic controllers. IC Role / Device Role / Timing Role: Persistent parameter store updated only during commissioning or maintenance mode; accessed via I²C during boot sequence. Use Value: Guarantees deterministic startup behavior after power loss; 1 µA standby current extends backup battery life in uninterruptible operation. |
| Medical Device Settings Retention | Automotive Body Control Module NVM |
Use Scenario: Saving patient-specific therapy settings (e.g., infusion rate, dose limits) in portable drug pumps with battery backup. IC Role / Device Role / Timing Role: Secure, tamper-resistant storage of safety-critical operational parameters; WP pin permanently tied to VCC during production. Use Value: Meets IEC 62304 Class C software requirements for data integrity; >200-year retention exceeds device lifetime expectations. |
Use Scenario: Holding door lock actuator profiles, mirror position memories, and lighting dimming curves in 12V automotive body electronics. IC Role / Device Role / Timing Role: Secondary NVM supplementing MCU flash for frequently updated user preferences; interfaces directly to 3.3V CAN/LIN subsystem MCUs. Use Value: 400 kHz I²C speed enables fast parameter loading during vehicle wake-up; AEC-Q100 qualification ensures reliability under automotive thermal cycling. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 24LC128-I/ST | Requires minimum 2.5V VCC; identical pinout, timing, and memory architecture | Not suitable for 1.8V systems; otherwise drop-in for legacy 3.3V/5V designs with no layout change | Select when operating exclusively above 2.5V and cost sensitivity outweighs low-voltage flexibility |
| AT24C128-10PU-2.7 | Same 128 Kbit capacity, 1 MHz I²C, but requires ≥2.7V; different WP polarity (active-low on some variants) | Lacks 1.7V support and AEC-Q100 qualification; higher clock speed benefits high-throughput logging | Prefer for new 3.3V designs needing faster writes, but verify WP pin behavior and qualification status for automotive use |
Compared with 24LC128-I/ST, the 24AA128-I/ST enables true single-supply operation down to 1.7V while maintaining identical packaging and I²C protocol compliance; versus AT24C128-10PU-2.7, it trades maximum clock speed for broader voltage range and automotive qualification - making it optimal for battery-constrained or safety-critical deployments.
Availability
24AA128-I/ST is available at Aetrix Electronics and suitable for industrial automation, medical instrumentation, and automotive body electronics requiring stable component supply, long-term lifecycle support, and RoHS-compliant sourcing.
Supply support for 24AA128-I/ST includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a U.S.-based semiconductor company specializing in microcontrollers, analog devices, and memory solutions, with global manufacturing and quality certifications including ISO 9001 and AEC-Q200.
The 24AA128 belongs to Microchip's 24XX128 family of I²C EEPROMs engineered for robust, low-power nonvolatile storage in harsh environments - targeting applications where data integrity, voltage flexibility, and long-term reliability are mandatory.
FAQ
What is the minimum operating voltage for the 24AA128-I/ST?
The 24AA128-I/ST operates down to 1.7V across its full industrial temperature range (–40°C to +85°C). This enables direct interface with 1.8V microcontrollers and energy-harvesting power supplies without level-shifting circuitry. The device maintains full I²C functionality, including 400 kHz clock support and reliable page writes, at this minimum voltage.
Does the 24AA128-I/ST support multi-device I²C bus configurations?
Yes, the 24AA128-I/ST supports cascading up to eight devices on a single I²C bus using hardware-configurable A2, A1, and A0 pins. Each device is assigned a unique 7-bit slave address (1010xxx) based on the logic levels applied to these pins. This allows expansion to 1 Mbit of contiguous address space when multiple 24AA128-I/ST units are deployed.
How does hardware write-protection work on the 24AA128-I/ST?
The WP pin on the 24AA128-I/ST provides hardware-level write inhibition: when tied to VCC, all write operations (byte and page) to the entire 128 Kbit array (addresses 0000h–3FFFh) are blocked, while read operations remain fully functional. The pin state is sampled at the Stop bit of each write command, ensuring protection cannot be overridden mid-cycle.
What is the maximum I²C clock frequency supported by the 24AA128-I/ST?
The 24AA128-I/ST supports up to 400 kHz I²C clock frequency when VCC is 2.5V or higher. At VCC < 2.5V, the maximum clock rate is 100 kHz. These limits are defined by AC timing parameters including THIGH (≥600 ns), TLOW (≥1300 ns), and TR/TF (≤300 ns), ensuring reliable communication across the specified voltage and temperature range.
Is the 24AA128-I/ST qualified for automotive applications?
Yes, the 24AA128-I/ST is AEC-Q100 qualified for automotive applications. It meets stress test requirements for temperature cycling, humidity bias, and ESD (≥4,000V HBM), and is rated for operation across the industrial temperature range (–40°C to +85°C), which aligns with AEC-Q100 Grade 3 specifications. This makes it suitable for body control modules and infotainment subsystems.
24AA128-I/ST Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 128Kbit
- Memory Organization:
- 16K x 8
- Memory Interface:
- I2C
- Clock Frequency:
- 400 kHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- 900 ns
- Voltage - Supply:
- 1.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
24AA128-I/ST FAQ
1.How can I place an order for 24AA128-I/ST through Aetrix?
Please submit a Request for Quotation (RFQ) for 24AA128-I/ST on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 24AA128-I/ST reliable?
The price and inventory of 24AA128-I/ST are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 24AA128-I/ST is usually 5 days.
3.What payment methods are accepted for 24AA128-I/ST?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 24AA128-I/ST transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 24AA128-I/ST?
24AA128-I/ST orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 24AA128-I/ST order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 24AA128-I/ST?
For technical support, including 24AA128-I/ST datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 24AA128-I/ST requirements.
6.How does Aetrix verify that 24AA128-I/ST is sourced from the original manufacturer or authorized distributors?
All 24AA128-I/ST products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 24AA128-I/ST meets industry standards.
7.What is the process for return or replacement of 24AA128-I/ST?
All 24AA128-I/ST units undergo pre-shipment inspection (PSI). If there is an issue with 24AA128-I/ST, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 24AA128-I/ST part is unused and in its original packaging.
Return procedure for 24AA128-I/ST:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
24AA128-I/ST Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
