Microchip Technology 24AA256UIDT-I/ST
- Part No.:
- 24AA256UIDT-I/ST
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
24AA256UIDT-I/ST.pdf
- Description:
- IC EEPROM 256KBIT I2C 8TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
24AA256UIDT-I/ST from Microchip Technology Inc. is a 32K × 8 (256 Kbit) I²C-compatible serial EEPROM with factory-programmed EUI-48™ and EUI-64™ node addresses plus a unique 32-bit serial number, operating from 1.7V to 5.5V, featuring 64-byte page write buffer, 400 µA typical active current, and industrial temperature range (–40°C to +85°C). It is used for secure device identification and persistent configuration storage in networked embedded systems.
For engineers reviewing the 24AA256UIDT-I/ST datasheet, 24AA256UIDT-I/ST pinout, 24AA256UIDT-I/ST application, or 24AA256UIDT-I/ST equivalent, this page delivers verified electrical specs, validated I²C timing compliance at 100 kHz/400 kHz, confirmed preprogrammed UID memory map, real-world endurance (1M cycles), and accurate TSSOP-8 package interface details - all critical for secure boot, asset tracking, and firmware anti-cloning designs.
Technical Context
The 24AA256UIDT-I/ST implements a standard two-wire I²C slave interface with Schmitt-trigger inputs and slope-controlled outputs to suppress noise and eliminate ground bounce. Its internal address pointer supports current-address, random, and sequential read modes, while the 64-byte page buffer enables efficient bulk writes within physical page boundaries (0x0000–0x003F, etc.).
Write protection is permanently enforced on the upper 1/8th of the array (0x7000–0x7FFF), where EUI-48 (0x7F7A–0x7F7F), EUI-64 (0x7FB8–0x7FBF), and the 32-bit serial number (0x7FFC–0x7FFF) reside alongside manufacturer code (0x7FFA = 0x29) and device identifier (0x7FFB = 0x48). Acknowledge polling is supported to detect write cycle completion without fixed delays.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 256 Kbit (32K × 8), providing sufficient space for firmware metadata, calibration data, and secure identifiers |
| Interface | I²C-compatible 2-wire bus, supporting standard-mode (100 kHz) and fast-mode (400 kHz) clock rates with full ACK/NACK protocol compliance |
| Supply Voltage | 1.7V to 5.5V operation enables direct integration with low-voltage MCUs and legacy 5V systems without level-shifting |
| Page Write Buffer | 64-byte buffer allows single-command writes up to one full page, reducing bus overhead and improving write throughput |
| Endurance & Retention | 1,000,000 erase/write cycles and >200 years data retention ensure long-term reliability in field-deployed assets |
| UID Storage | Factory-programmed 32-bit serial number (0x7FFC–0x7FFF), EUI-48 (0x7F7A–0x7F7F), and EUI-64 (0x7FB8–0x7FBF) stored in permanently write-protected region |
| ESD Protection | ≥4 kV HBM rating provides robust handling during board assembly and field service without additional protection circuitry |
Pinout & Package
24AA256UIDT-I/ST is housed in an 8-pin TSSOP package (3.0 mm × 4.4 mm, 0.65 mm pitch), RoHS-compliant and optimized for high-density PCB layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0 | Chip Address Input | User-configurable LSB of 3-bit slave address; hardwired to VSS or VCC to select one of eight possible I²C addresses (1010xxx0/1) |
| A1 | Chip Address Input | Mid-bit of slave address; determines device selection when multiple 24AA256UIDT-I/ST units share the same I²C bus |
| A2 | Chip Address Input | MSB of slave address; enables cascading up to eight devices with non-overlapping I²C addresses |
| VSS | Ground Reference | Primary return path for all internal logic and I/O; must be low-impedance connection to system GND plane |
| SDA | Serial Data Line | Open-drain bidirectional I²C data line requiring external pull-up (2 kΩ @ 400 kHz); changes only during SCL low except for START/STOP |
| SCL | Serial Clock Input | Input-only I²C clock line synchronized to master; includes Schmitt trigger for noise immunity and slope control to limit di/dt |
| NC | No Connect | Internally unconnected pin; must remain floating - no routing or soldering required |
| VCC | Power Supply | Single supply input (1.7V–5.5V); powers EEPROM core, UID registers, and I/O buffers; bypass capacitor (0.1 µF) recommended near pin |
Key Features
| Feature | Design Value |
|---|---|
| Globally Unique Node Addressing | EUI-48™ and EUI-64™ addresses preprogrammed at factory and guaranteed unique across all Microchip UID-family devices - eliminates MAC address collision in IoT deployments |
| Immutable Identity Storage | 32-bit serial number, manufacturer code (0x29), and device ID (0x48) stored in permanently write-protected upper 1/8th memory (0x7000–0x7FFF), preventing tampering or overwrite in field use |
| Low-Voltage Operation | Functional down to 1.7V enables direct interfacing with battery-powered or energy-harvesting microcontrollers without voltage translation |
| Robust Bus Interface | Schmitt-trigger inputs and controlled output slew rate suppress noise and prevent ground bounce - critical for noisy industrial or automotive environments |
| High-Reliability Nonvolatile Storage | 1 million write cycles and >200-year data retention meet stringent requirements for medical, industrial, and infrastructure equipment lifecycles |
Applications
| Secure Device Authentication | Firmware Anti-Cloning |
|---|---|
Use Scenario: Embedded gateway authenticates peripherals via IEEE EUI-64 before enabling communication channels. IC Role / Device Role / Timing Role: Provides cryptographically verifiable, immutable hardware identity as root-of-trust anchor for TLS certificate binding. Use Value: Eliminates need for external secure element by delivering factory-programmed, globally unique 64-bit node address with guaranteed uniqueness per IEEE standards. | Use Scenario: Industrial PLC verifies firmware signature against hash stored in EEPROM before boot. IC Role / Device Role / Timing Role: Stores cryptographic hash and version metadata in write-protected UID region, accessed early in boot sequence. Use Value: Prevents unauthorized firmware duplication using preprogrammed 32-bit serial number bound to device-specific keys - no runtime key generation required. |
| Asset Tracking & Calibration | Networked Sensor Node ID |
Use Scenario: Factory-calibrated pressure sensor retains NIST-traceable calibration coefficients and serial ID across power cycles. IC Role / Device Role / Timing Role: Holds calibrated offset/gain values and unique 32-bit serial number in user-accessible lower 229Kbit region, readable over I²C during initialization. Use Value: Enables full traceability from manufacturing to field deployment using factory-assigned serial number, eliminating manual labeling errors. | Use Scenario: Wireless environmental sensor broadcasts its EUI-48 address in BLE advertising packets for cloud registration. IC Role / Device Role / Timing Role: Supplies IEEE-compliant 48-bit MAC address directly from preprogrammed memory (0x7F7A–0x7F7F) during system startup. Use Value: Guarantees globally unique network identity without software-based randomization or risk of duplicate assignment in large-scale deployments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM with UID applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 24AA256-I/ST | Lacks factory-programmed EUI-48/EUI-64 and 32-bit serial number; identical memory size, interface, and package | Requires external UID management in firmware or separate secure element for device identity | Select only if UID functionality is unnecessary and cost sensitivity outweighs security and traceability benefits |
| AT24CM02-SSHD-T | 2 Mbit capacity, supports I²C up to 1 MHz, but no preprogrammed UID or EUI addresses; different page size (128 bytes) | Suitable for high-capacity logging but cannot replace 24AA256UIDT-I/ST in identity-critical roles like secure boot or regulatory asset tagging | Choose when raw storage density matters more than factory-assigned global uniqueness and IEEE-compliant addressing |
Compared with 24AA256-I/ST, the 24AA256UIDT-I/ST adds immutable identity features without sacrificing compatibility; versus AT24CM02-SSHD-T, it trades capacity for certified UID assurance - making it the sole choice where EUI-48/EUI-64 compliance and tamper-proof serial numbers are mandatory.
Availability
24AA256UIDT-I/ST is available at Aetrix Electronics and suitable for secure boot, asset tracking, and firmware anti-cloning applications requiring stable component supply across extended product lifecycles.
Supply support for 24AA256UIDT-I/ST includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog components, and memory solutions, headquartered in Chandler, Arizona, with global design and manufacturing operations.
The 24AA256UIDT-I/ST belongs to Microchip's UID-family of serial EEPROMs, designed specifically to deliver factory-programmed, globally unique identifiers for secure device authentication, regulatory compliance, and zero-touch provisioning in IoT and industrial networks.
FAQ
What is the exact memory organization of the 24AA256UIDT-I/ST, and where are the preprogrammed identifiers stored?
The 24AA256UIDT-I/ST contains 256 Kbit (32K × 8) of EEPROM organized linearly from 0x0000 to 0x7FFF. The upper 1/8th (0x7000–0x7FFF) is permanently write-protected. Within that region: EUI-48™ resides at 0x7F7A–0x7F7F, EUI-64™ at 0x7FB8–0x7FBF, and the 32-bit serial number at 0x7FFC–0x7FFF. Manufacturer code (0x29) and device ID (0x48) occupy 0x7FFA and 0x7FFB respectively. All these values are factory-programmed and immutable.
Does the 24AA256UIDT-I/ST support both 100 kHz and 400 kHz I²C clock speeds, and what determines the maximum frequency?
Yes, the 24AA256UIDT-I/ST supports both 100 kHz and 400 kHz I²C clock frequencies. The maximum allowed clock frequency depends on VCC: 100 kHz is guaranteed for VCC < 2.5V, while 400 kHz is supported for VCC ≥ 2.5V. This dual-speed capability ensures interoperability with legacy controllers and modern high-throughput masters without redesigning the bus timing.
How does write protection work on the 24AA256UIDT-I/ST, and can it be disabled?
Write protection on the 24AA256UIDT-I/ST is permanent and hardware-enforced for the upper 1/8th of the memory array (0x7000–0x7FFF), where all preprogrammed identifiers reside. This region cannot be unlocked or modified under any condition - no command, voltage sequence, or fuse-setting can disable it. The remaining 229,376 bits (0x0000–0x6FFF) are fully writable and readable using standard I²C byte/page write commands.
What package type is used for the 24AA256UIDT-I/ST, and what are its key mechanical dimensions?
The 24AA256UIDT-I/ST uses an 8-pin TSSOP package (Microchip drawing C04-057-SN Rev D), measuring 3.0 mm × 4.4 mm with 0.65 mm lead pitch. It features a nominal body thickness of 1.0 mm and a maximum height of 1.2 mm. The package is RoHS-compliant, lead-free, and marked with "AAAP", year/week code, and traceability characters - matching the "T" suffix in the part number.
Can multiple 24AA256UIDT-I/ST devices share the same I²C bus, and how is addressing managed?
Yes, up to eight 24AA256UIDT-I/ST devices can share a single I²C bus using hardware address pins A0, A1, and A2. These three pins form the three LSBs of the 7-bit slave address (base 0x50), allowing unique addresses from 0x50 to 0x57. Each device must have a distinct combination of A0–A2 tied to VSS or VCC; floating pins are not permitted. This enables scalable, deterministic addressing without software arbitration.
24AA256UIDT-I/ST Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- I2C
- Clock Frequency:
- 400 kHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- 900 ns
- Voltage - Supply:
- 1.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
24AA256UIDT-I/ST FAQ
1.How can I place an order for 24AA256UIDT-I/ST through Aetrix?
Please submit a Request for Quotation (RFQ) for 24AA256UIDT-I/ST on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 24AA256UIDT-I/ST reliable?
The price and inventory of 24AA256UIDT-I/ST are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 24AA256UIDT-I/ST is usually 5 days.
3.What payment methods are accepted for 24AA256UIDT-I/ST?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 24AA256UIDT-I/ST transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 24AA256UIDT-I/ST?
24AA256UIDT-I/ST orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 24AA256UIDT-I/ST order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 24AA256UIDT-I/ST?
For technical support, including 24AA256UIDT-I/ST datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 24AA256UIDT-I/ST requirements.
6.How does Aetrix verify that 24AA256UIDT-I/ST is sourced from the original manufacturer or authorized distributors?
All 24AA256UIDT-I/ST products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 24AA256UIDT-I/ST meets industry standards.
7.What is the process for return or replacement of 24AA256UIDT-I/ST?
All 24AA256UIDT-I/ST units undergo pre-shipment inspection (PSI). If there is an issue with 24AA256UIDT-I/ST, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 24AA256UIDT-I/ST part is unused and in its original packaging.
Return procedure for 24AA256UIDT-I/ST:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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