Microchip Technology 24LC02BH-E/P
- Part No.:
- 24LC02BH-E/P
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-DIP (0.300", 7.62mm)
- Datasheet:
-
24LC02BH-E/P.pdf
- Description:
- IC EEPROM 2KBIT I2C 400KHZ 8DIP
- Quantity:
- Payment:

- Shipping:

Inventory:4,347
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Product details
Overview
24LC02BH-E/P from Microchip Technology Inc. is a 2 Kbit I²C-compatible serial EEPROM organized as 256 × 8-bit memory with hardware write-protect for the upper half-array (80h–FFh), 400 kHz max clock frequency at VCC ≥ 2.5 V, and operation over –40°C to +125°C (Extended temperature grade). It supports page writes up to 8 bytes, features Schmitt-trigger inputs and slope-controlled outputs, and is used in industrial sensor calibration storage and embedded system configuration retention.
For engineers reviewing the 24LC02BH-E/P datasheet, 24LC02BH-E/P pinout, 24LC02BH-E/P application, or 24LC02BH-E/P equivalent, key selection considerations include its 2.5–5.5 V supply range, half-array write-protection logic via WP pin, 5 ms max page write time, and compatibility with I²C bus timing requirements for both 100 kHz and 400 kHz modes.
Technical Context
The 24LC02BH-E/P implements a two-wire I²C interface with fixed 7-bit device address (1010xxx) and R/W bit control, supporting byte and page write operations with automatic internal erase/write cycle timing. Its Address Pointer increments on each read or write, enabling sequential access across the full 256-byte array.
Hardware write-protection is implemented via the WP pin: tied to VCC, it disables writes to addresses 0x80–0xFF while allowing full read access; tied to VSS, full read/write capability is enabled. The A0–A2 pins are unconnected and may be left floating or tied to either rail without effect.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 2 Kbit (256 × 8-bit), sufficient for storing calibration coefficients, device IDs, or small firmware parameters in space-constrained designs. |
| VCC Range | 2.5 V to 5.5 V - compatible with 3.3 V and 5 V systems; no operation below 2.5 V (unlike 24AA02H). |
| Max Clock Frequency | 400 kHz at VCC ≥ 2.5 V - enables faster configuration loading vs. legacy 100 kHz EEPROMs; timing validated per I²C Fast-mode spec. |
| Write Cycle Time | 5 ms maximum (byte or page) - defines minimum inter-write delay; self-timed, eliminating need for external polling wait states in most cases. |
| Endurance & Retention | 1 million erase/write cycles and >200 years data retention - suitable for infrequently updated but mission-critical nonvolatile storage. |
| Temperature Range | –40°C to +125°C (Extended grade) - qualified for under-hood automotive, industrial motor drives, and high-ambient environments. |
| ESD Protection | >4 kV HBM - robust against handling and board-level ESD events without external protection circuitry. |
Pinout & Package
24LC02BH-E/P is supplied in an 8-lead PDIP (Plastic Dual In-Line Package) with 300 mil body width. Pin 1 is marked by a notch or dot; leads are tin-plated matte finish per JEDEC J-STD-020.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0, A1, A2 | Device Address Inputs | No internal connection; unused - may be left floating or tied to VSS/VCC without affecting function or I²C address (fixed at 1010xxx). |
| VSS | Ground Reference | Primary return path for all internal circuits; must be low-impedance and decoupled near VCC pin. |
| SDA | Serial Data I/O | Open-drain bidirectional bus line requiring external pull-up (2 kΩ typical for 400 kHz); changes only during SCL low except for Start/Stop conditions. |
| SCL | Serial Clock Input | Input-only clock line synchronized to host controller; Schmitt-trigger input ensures noise immunity on slow-rising edges. |
| WP | Write-Protect Control | Logic-high (VCC) enables half-array protection (80h–FFh); logic-low (VSS) enables full-array write access. |
| VCC | Power Supply | 2.5–5.5 V supply; must be stable during write cycles; decoupling capacitor (0.1 µF ceramic) required adjacent to pin. |
Key Features
| Feature | Design Value |
|---|---|
| Half-Array Hardware Write-Protection | WP pin physically disables writes to upper 128 bytes (80h–FFh), preserving critical firmware or calibration data even during software faults. |
| 8-Byte Page Write Buffer | Reduces I²C bus occupancy by up to 8× vs. byte writes - improves system responsiveness when updating multi-byte configuration blocks. |
| Schmitt Trigger Inputs + Slope Control | Eliminates ground bounce and suppresses bus noise spikes >50 ns, enabling reliable operation on long or noisy PCB traces without added filtering. |
| I²C Bus Compatibility (100/400 kHz) | Supports both Standard- and Fast-mode timing, allowing drop-in replacement in existing 100 kHz designs while enabling bandwidth upgrades where host permits. |
| Low-Power Operation | 1 µA max standby current and 1 mA max active read current extend battery life in always-on sensor nodes and portable equipment. |
Applications
| Industrial Sensor Calibration Storage | Automotive Body Control Module (BCM) Configuration |
|---|---|
|
Use Scenario: Storing factory-calibrated offset/gain values for temperature, pressure, or current sensors in programmable logic controllers and process transmitters. IC Role / Device Role / Timing Role: Nonvolatile configuration register holding persistent sensor trim data accessed at power-up or during field recalibration. Use Value: Enables traceable, field-updatable calibration without requiring MCU code changes or external programming fixtures. |
Use Scenario: Retaining user-configurable settings (e.g., door lock behavior, mirror position memory, lighting profiles) in automotive BCMs operating across extended temperature ranges. IC Role / Device Role / Timing Role: Dedicated configuration EEPROM interfaced directly to BCM microcontroller via I²C for fast, deterministic parameter reads during boot. Use Value: Meets AEC-Q100 Grade 1 requirements and provides >200-year data retention for lifetime vehicle use without refresh. |
| Medical Device Parameter Backup | Smart Energy Meter Firmware Patch Storage |
|
Use Scenario: Saving therapy parameters (e.g., infusion rate limits, alarm thresholds) in portable insulin pumps and infusion devices requiring regulatory-compliant data persistence. IC Role / Device Role / Timing Role: Safety-critical nonvolatile memory with hardware write-protect to prevent accidental overwrite of validated clinical settings. Use Value: Half-array protection isolates immutable safety parameters (upper 128 bytes) from user-modifiable fields (lower 128 bytes), simplifying functional safety validation. |
Use Scenario: Storing field-deployed firmware patches or tariff tables in utility-grade smart meters exposed to outdoor ambient extremes. IC Role / Device Role / Timing Role: Secure, tamper-resistant update storage accessible only during authenticated bootloader sessions via I²C. Use Value: 1M-cycle endurance supports frequent patch deployments over 10+ year meter lifetime; 125°C rating ensures reliability inside sealed meter enclosures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 24AA02H-I/P | Wider VCC range (1.7–5.5 V); supports 100 kHz down to 1.7 V; same pinout and memory map. | Preferred for battery-powered devices operating below 2.5 V (e.g., coin-cell IoT sensors); not rated for 125°C. | Select 24AA02H-I/P if supply voltage may dip below 2.5 V; otherwise, 24LC02BH-E/P offers superior high-temp performance. |
| AT24C02D-SSHM-T | Same 2 Kbit capacity, 1.7–5.5 V range, and I²C interface; AEC-Q100 qualified; different pinout (SOIC-8 only) and no hardware WP pin. | Lacks half-array write-protection; requires software-based protection schemes; broader package availability (TDFN, UDFN). | Choose AT24C02D-SSHM-T only if WP functionality is unnecessary and SOIC-8 footprint is mandatory; verify timing compliance for 400 kHz operation. |
Compared with 24AA02H-I/P and AT24C02D-SSHM-T, the 24LC02BH-E/P uniquely combines extended temperature operation (–40°C to +125°C), hardware half-array write-protection, and guaranteed 400 kHz timing at 2.5 V - making it optimal for automotive and industrial applications where environmental robustness and data integrity are critical.
Availability
24LC02BH-E/P is available at Aetrix Electronics and suitable for industrial sensor calibration storage, automotive body control module configuration, and medical device parameter backup requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 24LC02BH-E/P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog components, and memory solutions, headquartered in Chandler, Arizona, with global design, manufacturing, and sales operations.
The 24LC02BH belongs to Microchip's serial EEPROM product line, designed specifically for reliable, low-power, I²C-based nonvolatile data storage in automotive, industrial, and medical applications demanding extended temperature operation and hardware-level data protection.
FAQ
What is the minimum operating voltage for the 24LC02BH-E/P?
The 24LC02BH-E/P requires a minimum VCC of 2.5 V and operates up to 5.5 V. Unlike the 24AA02H variant, it does not support operation below 2.5 V - attempting to power it at 1.8 V will result in undefined behavior or failure to respond on the I²C bus.
Does the 24LC02BH-E/P require external pull-up resistors on SDA and SCL lines?
Yes, the 24LC02BH-E/P has open-drain SDA and SCL pins and requires external pull-up resistors. For 400 kHz operation, a 2 kΩ resistor to VCC is recommended; for 100 kHz, 10 kΩ is typical. Values must be selected based on bus capacitance and rise-time requirements per I²C specification.
How does the WP pin affect memory access in the 24LC02BH-E/P?
When WP is tied to VCC, writes to addresses 0x80–0xFF are inhibited; reads remain fully functional across the entire 256-byte array. When WP is tied to VSS, full read/write access is enabled. This hardware-level protection prevents accidental overwrites without MCU intervention.
Can the 24LC02BH-E/P be used as a direct replacement for the 24LC02B-I/P?
No - the 24LC02BH-E/P is not a direct replacement for the older 24LC02B-I/P. While pin-compatible, the "H" suffix denotes enhanced features including Schmitt-trigger inputs, slope-controlled outputs, and improved ESD protection (>4 kV vs. <2 kV), and the "E" grade extends operation to +125°C versus +85°C for the "I" grade.
What is the maximum number of bytes that can be written in a single page write operation for the 24LC02BH-E/P?
The 24LC02BH-E/P supports an 8-byte page write buffer. Attempting to write more than 8 bytes before issuing a Stop condition causes the Address Pointer to roll over within the same physical page, overwriting previously loaded data - software must enforce page boundaries (0x00–0x07, 0x08–0x0F, etc.) to avoid corruption.
24LC02BH-E/P Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 2Kbit
- Memory Organization:
- 256 x 8
- Memory Interface:
- I2C
- Clock Frequency:
- 400 kHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- 900 ns
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 8-PDIP
24LC02BH-E/P FAQ
1.How can I place an order for 24LC02BH-E/P through Aetrix?
Please submit a Request for Quotation (RFQ) for 24LC02BH-E/P on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 24LC02BH-E/P reliable?
The price and inventory of 24LC02BH-E/P are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 24LC02BH-E/P is usually 5 days.
3.What payment methods are accepted for 24LC02BH-E/P?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 24LC02BH-E/P transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 24LC02BH-E/P?
24LC02BH-E/P orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 24LC02BH-E/P order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 24LC02BH-E/P?
For technical support, including 24LC02BH-E/P datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 24LC02BH-E/P requirements.
6.How does Aetrix verify that 24LC02BH-E/P is sourced from the original manufacturer or authorized distributors?
All 24LC02BH-E/P products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 24LC02BH-E/P meets industry standards.
7.What is the process for return or replacement of 24LC02BH-E/P?
All 24LC02BH-E/P units undergo pre-shipment inspection (PSI). If there is an issue with 24LC02BH-E/P, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 24LC02BH-E/P part is unused and in its original packaging.
Return procedure for 24LC02BH-E/P:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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