Microchip Technology 24LC1025-I/SM
- Part No.:
- 24LC1025-I/SM
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.209", 5.30mm Width)
- Datasheet:
-
24LC1025-I/SM.pdf
- Description:
- IC EEPROM 1MBIT I2C 400KHZ 8SOIJ
- Quantity:
- Payment:

- Shipping:

Inventory:3,940
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
24LC1025-I/SM from Microchip Technology Inc. is a 128K × 8 (1024 kbit) I²C-compatible serial EEPROM with industrial temperature range (−40°C to +85°C), 2.5–5.5 V supply voltage, and 400 kHz maximum clock frequency. It features 128-byte page write buffer, hardware write-protection via WP pin, and Schmitt-trigger inputs for noise immunity. It is used in embedded systems for nonvolatile storage of calibration data, configuration parameters, and firmware metadata.
For engineers reviewing the 24LC1025-I/SM datasheet, 24LC1025-I/SM pinout, 24LC1025-I/SM application, or 24LC1025-I/SM equivalent, key selection criteria include its 400 kHz I²C speed at 2.5–5.5 V, 5 µA standby current, 128-byte page write capability, and SOIJ-8 package compatibility with space-constrained industrial control modules.
Technical Context
The 24LC1025-I/SM implements a two-wire I²C interface with slave address decoding using A0/A1 pins and fixed A2 tied to VCC, enabling up to four devices on one bus. Its internal architecture includes a 128-byte page latch, EEPROM array segmented into two 512 kbit blocks (00000h–0FFFFh and 10000h–1FFFFh), and address pointer auto-increment for sequential reads.
Write operations support byte and page modes with self-timed erase/write cycles (typ. 3 ms, max 5 ms). The device uses Schmitt-trigger inputs on SDA/SCL (hysteresis ≥0.05 VCC) and slope-controlled outputs to suppress ground bounce - critical for reliable operation in noisy industrial environments.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 128K × 8 (1024 kbit); supports dual 512 kbit address blocks for modular firmware partitioning |
| Supply voltage | 2.5–5.5 V; compatible with standard 3.3 V and 5 V logic rails without level shifting |
| I²C clock speed | Up to 400 kHz (at VCC ≥ 2.5 V); enables faster parameter updates than 100 kHz legacy EEPROMs |
| Page write buffer | 128 bytes; reduces write transaction count by >90% vs. byte-write for configuration blocks |
| Standby current | ≤5 µA; extends battery life in always-on monitoring nodes and low-power IoT edge devices |
| Data retention | >200 years; ensures long-term integrity of calibration coefficients in field-deployed equipment |
| Endurance | 1 million erase/write cycles per page; supports frequent logging in data acquisition systems |
Pinout & Package
24LC1025-I/SM is housed in an 8-lead SOIJ (Small Outline Integrated Circuit, J-bend) package, 5.28 mm wide, RoHS-compliant and Pb-free. Pin 1 is A0 (chip select), pin 8 is VCC, and pin 3 (A2) must be hard-wired to VCC for guaranteed operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0 | Chip address input | User-configurable LSB of slave address; enables multi-device I²C bus expansion (up to 4 devices) |
| A1 | Chip address input | User-configurable MSB of slave address; combined with A0, selects one of four possible device addresses |
| A2 | Non-configurable chip select | Must be tied to VCC; floating or grounded A2 causes undefined behavior and functional failure |
| VSS | Ground reference | Common return path for all internal circuitry; requires low-impedance connection to system GND plane |
| SDA | Serial data bidirectional line | Open-drain I²C data line requiring external pull-up (2 kΩ typical for 400 kHz); supports ACK/NACK signaling |
| SCL | Serial clock input | Master-generated clock; rising edge samples SDA, falling edge allows SDA transitions per I²C protocol |
| WP | Hardware write-protect input | Logic high (VCC) disables all writes; logic low (VSS) enables full read/write access - critical for field firmware safety |
| VCC | Power supply | 2.5–5.5 V DC input; powers EEPROM core, I/O buffers, and internal charge pump for write operations |
Key Features
| Feature | Design Value |
|---|---|
| 128-byte page write buffer | Reduces I²C transaction overhead by batching up to 128 bytes per Stop condition, cutting bus utilization and host CPU load |
| Schmitt-trigger inputs on SDA/SCL | Provides ≥50 ns noise spike suppression and ≥0.05 VCC hysteresis, eliminating false Start/Stop detection in electrically noisy factory environments |
| Hardware write-protect (WP pin) | Enables fail-safe firmware update workflows: WP = VCC during normal operation prevents accidental overwrites of critical calibration tables |
| Dual 512 kbit address blocks | Allows independent access to two memory regions (00000h–0FFFFh and 10000h–1FFFFh) for active/inactive firmware bank switching |
| Self-timed write cycle | Eliminates need for host MCU to manage write timing; ACK polling confirms completion, enabling concurrent task execution |
Applications
| Industrial Sensor Calibration | Medical Device Configuration |
|---|---|
Use Scenario: Storing factory-calibrated sensor offset/gain coefficients and temperature compensation curves in programmable logic controllers. IC Role / Device Role / Timing Role: Nonvolatile parameter storage with guaranteed 200+ year data retention and 1M-cycle endurance for periodic recalibration events. Use Value: Eliminates manual trim potentiometers and enables automated calibration traceability across production batches. | Use Scenario: Holding user-selectable therapy parameters (e.g., infusion rate, alarm thresholds) and device serialization data in portable infusion pumps. IC Role / Device Role / Timing Role: Secure, tamper-resistant configuration storage with hardware write-protection (WP pin) to prevent unauthorized parameter changes. Use Value: Meets IEC 62304 Class C software requirements for persistent data integrity and audit-ready parameter history. |
| Automotive Body Control Module | Smart Energy Meter Firmware |
Use Scenario: Saving seat/mirror position presets, lighting profiles, and door lock settings in automotive BCMs operating across −40°C to +85°C. IC Role / Device Role / Timing Role: Industrial-grade EEPROM with extended temperature rating and 400 kHz I²C speed for real-time user preference recall. Use Value: Enables zero-latency recall of stored settings after ignition cycle without relying on volatile RAM backup capacitors. | Use Scenario: Storing tariff schedules, meter ID, firmware version, and cryptographic keys in ANSI C12.22-compliant smart meters. IC Role / Device Role / Timing Role: High-reliability nonvolatile memory with ESD protection >4 kV and 128-byte page writes for secure firmware update staging. Use Value: Supports encrypted OTA updates with atomic page-level writes, preventing partial corruption during power loss. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 24AA1025-I/SM | Wider VCC range (1.7–5.5 V); supports 100 kHz only below 2.5 V; same SOIJ-8 package and pinout | Preferred for 1.8 V or 2.5 V systems where 24LC1025-I/SM is out-of-spec | Select when operating below 2.5 V or needing broader supply tolerance; verify I²C speed constraints per VCC |
| AT24C1024-MAHM-T | Same 1024 kbit density and SOIJ-8 package; 1 MHz max clock (at 2.5–5.5 V); different slave address mapping (A0/A1 only) | Better suited for high-throughput logging where 400 kHz is insufficient; no A2 pin dependency | Choose for faster write throughput; note absence of A2 pin - simplifies layout but removes 4-device cascading capability |
Compared with 24LC1025-I/SM, 24AA1025-I/SM offers lower-voltage operation at reduced speed, while AT24C1024-MAHM-T delivers higher bandwidth but lacks A2-based multi-device addressing - making 24LC1025-I/SM optimal for robust, cascaded industrial I²C networks.
Availability
24LC1025-I/SM is available at Aetrix Electronics and suitable for industrial automation, medical instrumentation, and automotive body electronics requiring stable component supply, long-lifecycle support, and guaranteed RoHS compliance.
Supply support for 24LC1025-I/SM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog components, and memory solutions, headquartered in Chandler, Arizona, with global design and manufacturing operations.
The 24LC1025 belongs to Microchip's 24XX1025 family of I²C EEPROMs, engineered for high-reliability nonvolatile storage in industrial, automotive, and medical applications demanding extended temperature operation and proven data integrity.
FAQ
What is the required VCC range for reliable operation of the 24LC1025-I/SM?
The 24LC1025-I/SM operates reliably within a VCC range of 2.5 V to 5.5 V. Operation below 2.5 V is not supported and may result in undefined behavior, including failed writes or incorrect address decoding. This specification is explicitly defined in the Device Selection Table and Electrical Characteristics section of the official Microchip datasheet DS20001941L.
Can the 24LC1025-I/SM be used in a 100 kHz I²C system?
Yes, the 24LC1025-I/SM supports 100 kHz I²C operation, but only under specific conditions: it is rated for 100 kHz when VCC < 4.5 V in industrial temperature range, and also supports 100 kHz across its full VCC range if system timing margins permit. The device guarantees 400 kHz operation at VCC ≥ 2.5 V, making 100 kHz fully compatible for legacy or noise-sensitive designs.
Is the A2 pin on the 24LC1025-I/SM configurable like A0 and A1?
No - the A2 pin on the 24LC1025-I/SM is non-configurable and must be hard-wired to VCC for proper operation. Unlike A0 and A1, which serve as user-defined chip address bits, A2 is a fixed enable signal. If left floating or tied to VSS, the device enters an undefined state and will not respond to I²C commands, as confirmed in Section 2.2 of the datasheet.
How does the 24LC1025-I/SM handle page boundary crossing during a page write?
The 24LC1025-I/SM does not wrap writes across physical page boundaries. If a page write command attempts to cross a 128-byte boundary (e.g., writing from address 0x007F to 0x0080), data wraps back to the start of the current page and overwrites prior bytes. This behavior is documented in Section 6.3 and requires firmware to split writes at page boundaries - a critical design constraint for reliable data storage.
What is the maximum number of 24LC1025-I/SM devices that can share one I²C bus?
Up to four 24LC1025-I/SM devices can be cascaded on a single I²C bus using unique combinations of A0 and A1 logic levels. Each device responds only to its assigned 7-bit slave address (1010xx0), where 'xx' corresponds to A1/A0 states. A2 is not used for addressing and must be tied high on all units - this configuration is validated in the Device Selection Table and Functional Description sections.
24LC1025-I/SM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.209", 5.30mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 1Mbit
- Memory Organization:
- 128K x 8
- Memory Interface:
- I2C
- Clock Frequency:
- 400 kHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- 900 ns
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIJ
24LC1025-I/SM FAQ
1.How can I place an order for 24LC1025-I/SM through Aetrix?
Please submit a Request for Quotation (RFQ) for 24LC1025-I/SM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 24LC1025-I/SM reliable?
The price and inventory of 24LC1025-I/SM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 24LC1025-I/SM is usually 5 days.
3.What payment methods are accepted for 24LC1025-I/SM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 24LC1025-I/SM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 24LC1025-I/SM?
24LC1025-I/SM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 24LC1025-I/SM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 24LC1025-I/SM?
For technical support, including 24LC1025-I/SM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 24LC1025-I/SM requirements.
6.How does Aetrix verify that 24LC1025-I/SM is sourced from the original manufacturer or authorized distributors?
All 24LC1025-I/SM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 24LC1025-I/SM meets industry standards.
7.What is the process for return or replacement of 24LC1025-I/SM?
All 24LC1025-I/SM units undergo pre-shipment inspection (PSI). If there is an issue with 24LC1025-I/SM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 24LC1025-I/SM part is unused and in its original packaging.
Return procedure for 24LC1025-I/SM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
24LC1025-I/SM Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

