My Inquiry
My Account
Microchip Technology 24LC128-I/MF
- Part No.:
- 24LC128-I/MF
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-VDFN Exposed Pad
- Datasheet:
-
24LC128-I/MF.pdf
- Description:
- IC EEPROM 128KBIT I2C 8DFN
- Quantity:
- Payment:
- Shipping:
Inventory:340
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
24LC128-I/MF from Microchip Technology Inc. is a 128 Kbit (16K × 8) I²C-compatible serial EEPROM designed for nonvolatile data storage in low-power embedded systems. It operates from 2.5V to 5.5V, supports up to 400 kHz I²C clock frequency, features hardware write-protection via the WP pin, and delivers 1 million erase/write cycles with >200 years data retention. It is used in industrial sensor calibration, power meter configuration, and firmware parameter storage.
For engineers reviewing the 24LC128-I/MF datasheet, 24LC128-I/MF pinout, 24LC128-I/MF application, or 24LC128-I/MF equivalent, this page provides verified electrical specs, package mapping to 8-lead DFN (MF), I²C timing constraints at 2.5–5.5V, and confirmed alternatives for industrial-grade serial EEPROM replacement.
Technical Context
The 24LC128-I/MF implements a two-wire I²C slave interface with Schmitt-trigger inputs on SDA and SCL for noise immunity, slope-controlled outputs to suppress ground bounce, and a 64-byte page write buffer. Its internal address counter enables sequential reads across the full 128Kbit memory space (0x0000–0x3FFF).
It uses cascaded device addressing via A0/A1/A2 pins-supporting up to eight devices on one bus-and integrates hardware write protection activated when WP = VCC. The device performs self-timed erase/write cycles with no external timing components required.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 128 Kbit (16,384 × 8 bits), mapped linearly from 0x0000 to 0x3FFF |
| VCC range | 2.5V to 5.5V - limits use to systems with ≥2.5V supply; not compatible with 1.7–2.49V rails |
| I²C clock max | 400 kHz - defines maximum bus throughput; requires pull-up resistors ≤2 kΩ at 5V |
| Page write buffer | 64 bytes - enables burst writes within one physical page (0–63, 64–127, etc.) without rollover risk |
| Write endurance | 1,000,000 cycles - specified per page; page-level wear leveling required for longevity |
| Data retention | >200 years at +25°C - validated under industrial temperature stress; derates at elevated TA |
| Standby current | 1 µA max (I-temp) - enables battery-backed operation in always-on monitoring nodes |
Pinout & Package
24LC128-I/MF is packaged in an 8-lead DFN (Dual Flat No-lead) with exposed thermal pad, designated by suffix "MF" per Microchip's marking standard (DS20001191T-page 15). Pin 1 is marked by a dot or beveled corner; the exposed pad may be connected to VSS or left floating.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0 | Chip address input | LSB of 3-bit slave address; hardwired to VSS or VCC to configure I²C address (1010xx0) |
| A1 | Chip address input | Middle bit of slave address; determines device select among up to eight 24LC128 units on same bus |
| A2 | Chip address input | MSB of slave address; sets unique I²C address; required for multi-device cascading |
| VSS | Ground reference | Return path for all internal logic and I/O; must be low-impedance connection to system GND |
| SDA | Serial data I/O | Open-drain bidirectional line; requires external pull-up; carries address, data, and ACK/NACK |
| SCL | Serial clock input | Master-generated clock; synchronizes all I²C transfers; edge-sensitive timing critical for compliance |
| WP | Hardware write-protect | Active-high enable: tied to VCC blocks all writes while permitting unlimited reads |
| VCC | Power supply | Primary voltage rail (2.5–5.5V); powers EEPROM array, control logic, and I/O buffers |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger inputs | 5% VCC hysteresis on SDA/SCL - rejects noise spikes ≤50 ns, eliminating need for external filtering |
| Output slope control | Controlled rise/fall times - prevents ground bounce during fast transitions, improving signal integrity |
| Page write capability | 64-byte buffer - reduces I²C transaction count by 64× vs. byte-write; cuts bus overhead and latency |
| Hardware write-protect | Dedicated WP pin - enables field-safe firmware updates without software lockout risk or code changes |
| Cascadable architecture | 3 address pins (A0–A2) - supports up to eight devices on single I²C bus, expanding total address space to 1 Mbit |
Applications
| Industrial Sensor Calibration | Smart Energy Metering |
|---|---|
|
Use Scenario: Storing factory-trimmed offset/gain coefficients for analog sensor front-ends in programmable logic controllers. IC Role / Device Role / Timing Role: Nonvolatile configuration storage accessed at power-up; read-only during runtime; WP pin held high after calibration. Use Value: Eliminates recalibration during field deployment; retains values across 10+ year product lifecycle without backup battery. |
Use Scenario: Recording tariff schedules, demand thresholds, and tamper-event logs in DIN-rail mounted electricity meters. IC Role / Device Role / Timing Role: High-reliability data logger with guaranteed 1M write cycles; writes triggered by metering IC interrupts. Use Value: Survives 10,000+ daily write events over 10 years; meets IEC 62056-21 data integrity requirements. |
| Medical Device Configuration | Automotive Body Control Module |
|
Use Scenario: Saving user-defined therapy parameters (e.g., pressure settings, alarm thresholds) in portable respiratory equipment. IC Role / Device Role / Timing Role: Secure parameter store with WP-enabled lockdown post-configuration; accessed via isolated I²C bus. Use Value: Prevents accidental overwrite during clinical use; supports FDA-required audit trail via timestamped write logging. |
Use Scenario: Storing seat/mirror position presets, lighting profiles, and diagnostic fault codes in 12V automotive BCMs. IC Role / Device Role / Timing Role: Automotive-grade EEPROM interfacing directly to MCU I²C peripheral; operates across -40°C to +85°C. Use Value: Qualified to AEC-Q100 Grade 2; withstands load-dump transients when powered via local LDO. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 24AA128-I/MF | Wider VCC range (1.7–5.5V); supports 100 kHz @ 1.7–2.49V; identical pinout and command set | Enables direct use in 1.8V microcontroller systems where 24LC128-I/MF cannot operate | Select when system VCC may dip below 2.5V or when mixed-voltage I²C bus design is required. |
| AT24C128-10PU-2.7 | Same 128 Kbit density and 8-lead PDIP package; 1 MHz max clock only above 2.7V; 400 kHz at 2.7V | Requires PCB layout change (PDIP vs. DFN); lacks AEC-Q100 qualification; lower ESD rating (2 kV) | Choose for legacy through-hole designs or cost-sensitive non-automotive applications with 2.7V+ supply. |
Compared with 24LC128-I/MF, 24AA128-I/MF extends low-voltage operation but shares identical DFN footprint and industrial temp grade, while AT24C128-10PU-2.7 offers higher speed at 2.7V+ but sacrifices automotive qualification and package compatibility.
Availability
24LC128-I/MF is available at Aetrix Electronics and suitable for industrial sensor calibration, smart energy metering, and medical device configuration requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 24LC128-I/MF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog devices, and memory solutions, headquartered in Chandler, Arizona, with global manufacturing and support infrastructure.
The 24LC128 belongs to Microchip's 24XX128 family of I²C serial EEPROMs, engineered for robust, low-power nonvolatile storage in industrial, automotive, and medical applications demanding high endurance and long-term data integrity.
FAQ
What is the minimum operating voltage for 24LC128-I/MF?
The 24LC128-I/MF requires a minimum VCC of 2.5V and operates up to 5.5V. Unlike the 24AA128 variant, it is not rated for 1.7–2.49V operation. Attempting to power the 24LC128-I/MF below 2.5V may result in unreliable I²C communication or failed write cycles. Always verify supply stability within this range during brown-out conditions.
Does 24LC128-I/MF support 1 MHz I²C clock speed?
No, the 24LC128-I/MF is rated for up to 400 kHz I²C clock frequency across its full 2.5–5.5V VCC range. The 1 MHz capability is exclusive to the 24FC128 variant. Using 1 MHz with 24LC128-I/MF will violate AC timing specifications (e.g., THIGH, TLOW), causing communication failures or data corruption.
How many devices can be connected on the same I²C bus using 24LC128-I/MF?
Up to eight 24LC128-I/MF devices can share one I²C bus using unique combinations of A0, A1, and A2 pins tied to VSS or VCC. Each device responds only to its assigned 7-bit slave address (1010xx0 format). Note that the DFN package (MF) fully supports all three address pins - unlike the MSOP variant where A0/A1 are NC.
What happens if a page write crosses a 64-byte boundary in 24LC128-I/MF?
If a page write command attempts to write across a 64-byte physical page boundary (e.g., writing 65 bytes starting at address 0x003F), the address counter wraps within the current page. Data beyond byte 63 overwrites bytes 0–N in the same page instead of advancing to the next page. Application firmware must enforce page-aligned writes or split cross-boundary operations manually.
Is 24LC128-I/MF qualified for automotive applications?
Yes - the "I" in 24LC128-I/MF denotes Industrial temperature grade (-40°C to +85°C), and the device is explicitly AEC-Q100 qualified per the datasheet (DS20001191T-page 1). This makes it suitable for body electronics, infotainment, and ADAS subsystems where extended temperature operation and reliability validation are mandatory.
24LC128-I/MF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-VDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 128Kbit
- Memory Organization:
- 16K x 8
- Memory Interface:
- I2C
- Clock Frequency:
- 400 kHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- 900 ns
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-DFN-S (6x5)
24LC128-I/MF FAQ
1.How can I place an order for 24LC128-I/MF through Aetrix?
Please submit a Request for Quotation (RFQ) for 24LC128-I/MF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 24LC128-I/MF reliable?
The price and inventory of 24LC128-I/MF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 24LC128-I/MF is usually 5 days.
3.What payment methods are accepted for 24LC128-I/MF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 24LC128-I/MF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 24LC128-I/MF?
24LC128-I/MF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 24LC128-I/MF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 24LC128-I/MF?
For technical support, including 24LC128-I/MF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 24LC128-I/MF requirements.
6.How does Aetrix verify that 24LC128-I/MF is sourced from the original manufacturer or authorized distributors?
All 24LC128-I/MF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 24LC128-I/MF meets industry standards.
7.What is the process for return or replacement of 24LC128-I/MF?
All 24LC128-I/MF units undergo pre-shipment inspection (PSI). If there is an issue with 24LC128-I/MF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 24LC128-I/MF part is unused and in its original packaging.
Return procedure for 24LC128-I/MF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
24LC128-I/MF Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
