My Inquiry
My Account
Microchip Technology 24LC128-I/SN
- Part No.:
- 24LC128-I/SN
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
24LC128-I/SN.pdf
- Description:
- IC EEPROM 128KBIT I2C 8SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:10,992
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
24LC128-I/SN from Microchip Technology Inc. is a 128 Kbit (16K × 8) I²C-compatible serial EEPROM designed for nonvolatile data storage in low-power embedded systems. It operates from 2.5V to 5.5V, supports up to 400 kHz clock frequency, features hardware write-protection via the WP pin, and delivers 1 µA standby current at industrial temperature range (–40°C to +85°C). It is commonly used in metering calibration storage, sensor configuration retention, and firmware parameter backup.
For engineers reviewing the 24LC128-I/SN datasheet, 24LC128-I/SN pinout, 24LC128-I/SN application, or 24LC128-I/SN equivalent, key selection considerations include its 2.5V minimum VCC, 64-byte page write buffer, Schmitt-triggered SDA/SCL inputs for noise immunity, and compatibility with standard I²C master controllers across industrial temperature environments.
Technical Context
The 24LC128-I/SN implements a two-wire I²C slave interface with fixed 7-bit slave address prefix '1010' and user-configurable A2/A1/A0 bits enabling up to eight devices on one bus. Its internal architecture includes a 64-byte page latch, self-timed erase/write cycle, and address pointer that auto-increments during sequential reads.
It uses CMOS EEPROM technology with integrated high-voltage generator for write operations, Schmitt-trigger inputs on SDA and SCL for robust noise rejection, and slope-controlled outputs to suppress ground bounce. Write protection is implemented via a dedicated WP pin sampled at the Stop condition of each write command.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 128 Kbit (16,384 × 8), organized as 128 pages of 64 bytes each - enables efficient bulk configuration storage with page-level endurance management. |
| VCC Range | 2.5V to 5.5V - restricts use to systems with stable ≥2.5V supply; excludes ultra-low-voltage (1.7V–2.49V) applications supported by 24AA128/24FC128 variants. |
| Max Clock Frequency | 400 kHz - defines maximum I²C bus speed; not compatible with 1 MHz operation supported only by 24FC128. |
| Write Cycle Time | ≤5 ms per byte or page - determines minimum time between successive write commands; requires ACK polling or timeout-based synchronization. |
| Endurance | 1,000,000 write/erase cycles - specifies guaranteed reprogrammability per memory location before wear-out; applies to full-page writes. |
| Data Retention | 200 years at +25°C - ensures long-term integrity of stored calibration or security keys without refresh. |
| Temperature Range | –40°C to +85°C (Industrial grade) - validated for deployment in industrial control panels, automotive body modules, and outdoor IoT edge nodes. |
Pinout & Package
24LC128-I/SN is packaged in an 8-lead SOIC (SN) - narrow-body, 3.90 mm width, JEDEC MS-012AC compliant - with gull-wing leads, 1.27 mm pitch, and exposed pad not present (unlike DFN/TDFN variants).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0 | Chip Address Input | LSB of 3-bit device address; hardwired to VSS or VCC to configure one of eight possible I²C slave addresses (1010xxx0). |
| A1 | Chip Address Input | Middle bit of device address; enables multi-device bus topology without external logic or address decoding. |
| A2 | Chip Address Input | MSB of device address; allows up to eight 24LC128-I/SN units sharing one I²C bus with contiguous or disjoint address spaces. |
| VSS | Ground Reference | Primary return path for all internal circuitry and I/O; must be low-impedance to ensure noise margin for Schmitt-trigger inputs. |
| SDA | Serial Data I/O | Open-drain bidirectional line requiring external pull-up; carries address, data, and ACK/NACK signals per I²C protocol timing. |
| SCL | Serial Clock Input | Master-generated clock signal synchronizing all data transfers; rising edge samples data, falling edge permits data change. |
| WP | Hardware Write-Protect | Active-high enable: tied to VCC blocks all write operations (byte/page) while permitting unlimited reads - critical for firmware-safe field updates. |
| VCC | Power Supply | 2.5V–5.5V input powering EEPROM array, logic, and HV generator; decoupling capacitor (0.1 µF) required near pin for stability. |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger inputs on SDA/SCL | Provides 50 ns spike suppression and ≥0.05×VCC hysteresis - eliminates need for external RC filtering in electrically noisy industrial environments. |
| 64-byte page write buffer | Reduces write transaction overhead: up to 64 bytes committed per 5 ms cycle instead of 64 individual byte writes - improves system-level throughput by >10×. |
| Self-timed write cycle | Removes requirement for host MCU to manage precise timing; enables deterministic software flow using ACK polling instead of fixed delays. |
| Hardware write-protect (WP) | Prevents accidental overwrites during power transitions or firmware glitches - essential for storing immutable calibration constants or cryptographic keys. |
| I²C bus compatibility | Fully conforms to standard-mode (100 kHz) and fast-mode (400 kHz) I²C specifications - interoperable with legacy and modern microcontrollers without protocol translation. |
Applications
| Smart Energy Metering | Industrial PLC Configuration |
|---|---|
|
Use Scenario: Storing tariff tables, meter calibration coefficients, and tamper-event logs in electricity/water/gas meters operating unattended for 10+ years. IC Role / Device Role / Timing Role: Nonvolatile configuration store with 200-year data retention and 1M-cycle endurance - retains accuracy-critical parameters across power loss and firmware upgrades. Use Value: Eliminates battery-backed SRAM; reduces BOM cost and field failure risk from capacitor aging or leakage. |
Use Scenario: Holding I/O mapping, PID tuning parameters, and safety thresholds in programmable logic controllers deployed in factory automation lines. IC Role / Device Role / Timing Role: Industrial-grade EEPROM interfacing directly with ARM Cortex-M or Renesas RX MCUs via I²C - survives repeated parameter updates during commissioning and maintenance. Use Value: Enables zero-downtime reconfiguration without replacing controller hardware or requiring external programming tools. |
| Automotive Body Control Module | Medical Sensor Calibration |
|
Use Scenario: Saving seat/mirror position presets, lighting profiles, and door lock settings in AEC-Q100-compliant BCMs. IC Role / Device Role / Timing Role: Automotive-qualified EEPROM (I-temp rated) with 2.5V–5.5V operation - functions reliably across cold-crank (6.5V transients) and deep-sleep (2.5V battery) conditions. Use Value: Meets OEM requirements for data persistence over vehicle lifetime without supplemental power sources. |
Use Scenario: Storing factory-calibrated gain/offset values and sensor linearization coefficients in portable blood glucose monitors and pulse oximeters. IC Role / Device Role / Timing Role: Medical-grade nonvolatile memory with <1 µA standby current - extends battery life in Class II handheld diagnostics while preserving traceable calibration records. Use Value: Supports ISO 13485 compliance by providing immutable, timestamped calibration history accessible via I²C during device self-test. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 24AA128-I/SN | Supports 1.7V–5.5V VCC and 100 kHz (at <2.5V) / 400 kHz (≥2.5V); identical pinout and page size. | Enables battery-powered or energy-harvesting systems where supply may dip below 2.5V during brownout. | Select when system VCC can fall below 2.5V; verify I²C master supports dual-speed mode switching. |
| 24LC128-E/SN | Extended temperature range (–40°C to +125°C); same electrical specs but qualified for under-hood automotive use. | Required for engine control, transmission, or ADAS subsystems operating above +85°C ambient. | Choose for high-temperature environments; note higher standby current (5 µA vs. 1 µA) at E-temp. |
Compared with 24LC128-I/SN, 24AA128-I/SN adds low-voltage flexibility at the cost of no 1.7V support in this specific SN package variant, while 24LC128-E/SN trades industrial-grade power efficiency for extended thermal resilience - both require no PCB changes but differ in voltage and temperature validation scope.
Availability
24LC128-I/SN is available at Aetrix Electronics and suitable for smart metering, industrial PLCs, automotive body control modules, and medical sensor calibration requiring stable component supply across multi-year production cycles.
Supply support for 24LC128-I/SN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a U.S.-based semiconductor manufacturer specializing in microcontrollers, analog devices, and memory products, with global design centers and ISO 9001-certified wafer fabs.
The 24LC128 belongs to Microchip's 24XX128 family of I²C EEPROMs engineered for reliable, low-power nonvolatile storage in industrial, automotive, and consumer applications where data integrity and long-term retention are critical.
FAQ
What is the minimum supply voltage required for reliable operation of the 24LC128-I/SN?
The 24LC128-I/SN requires a minimum VCC of 2.5V for guaranteed functionality across its full industrial temperature range (–40°C to +85°C). Operation below 2.5V is not specified and may result in incomplete writes, read errors, or failure to acknowledge I²C commands. This distinguishes it from the 24AA128-I/SN, which supports down to 1.7V.
Does the 24LC128-I/SN support 1 MHz I²C communication?
No, the 24LC128-I/SN does not support 1 MHz I²C operation. Its maximum clock frequency is 400 kHz across the full 2.5V–5.5V VCC range. The 1 MHz capability is exclusive to the 24FC128 variant; using 24LC128-I/SN on a 1 MHz bus will cause communication failures due to violated timing margins (e.g., THIGH, TLOW, TR/TF).
How many devices can share the same I²C bus with the 24LC128-I/SN?
Up to eight 24LC128-I/SN devices can be cascaded on a single I²C bus using the A2, A1, and A0 address pins to generate unique 3-bit chip select codes (1010xxx0). Each device must have a distinct combination of these pins tied to VSS or VCC; duplicate addresses will cause bus contention and unpredictable ACK behavior.
What happens when the WP pin is held high during a write command to the 24LC128-I/SN?
When the WP pin is tied to VCC, the 24LC128-I/SN acknowledges the write command but performs no memory update - the addressed data remains unchanged. The device immediately accepts subsequent commands, enabling safe command-stream validation without risking corruption of protected configuration data.
Is the 24LC128-I/SN RoHS compliant and lead-free?
Yes, the 24LC128-I/SN is RoHS compliant and manufactured with lead-free terminations per Microchip's packaging specification. The SN package uses matte tin (Sn) plating, and the device meets JEDEC J-STD-020 moisture sensitivity level (MSL) 1 - suitable for standard reflow soldering without baking.
24LC128-I/SN Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 128Kbit
- Memory Organization:
- 16K x 8
- Memory Interface:
- I2C
- Clock Frequency:
- 400 kHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- 900 ns
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
24LC128-I/SN FAQ
1.How can I place an order for 24LC128-I/SN through Aetrix?
Please submit a Request for Quotation (RFQ) for 24LC128-I/SN on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 24LC128-I/SN reliable?
The price and inventory of 24LC128-I/SN are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 24LC128-I/SN is usually 5 days.
3.What payment methods are accepted for 24LC128-I/SN?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 24LC128-I/SN transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 24LC128-I/SN?
24LC128-I/SN orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 24LC128-I/SN order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 24LC128-I/SN?
For technical support, including 24LC128-I/SN datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 24LC128-I/SN requirements.
6.How does Aetrix verify that 24LC128-I/SN is sourced from the original manufacturer or authorized distributors?
All 24LC128-I/SN products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 24LC128-I/SN meets industry standards.
7.What is the process for return or replacement of 24LC128-I/SN?
All 24LC128-I/SN units undergo pre-shipment inspection (PSI). If there is an issue with 24LC128-I/SN, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 24LC128-I/SN part is unused and in its original packaging.
Return procedure for 24LC128-I/SN:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
24LC128-I/SN Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
