Microchip Technology 24LC128T-E/SN16KVAO
- Part No.:
- 24LC128T-E/SN16KVAO
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
24LC128T-E/SN16KVAO.pdf
- Description:
- IC EEPROM 128KBIT I2C 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:1,326
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
24LC128T-E/SN16KVAO from Microchip Technology is a 128 Kbit (16K × 8) I²C-compatible serial EEPROM with hardware write-protection, 64-byte page buffer, and industrial temperature range (–40°C to +85°C). It operates from 2.5V to 5.5V, supports up to 400 kHz clock frequency, and delivers ≤1 µA standby current - enabling low-power data logging in embedded sensor nodes and industrial controllers.
For engineers reviewing the 24LC128T-E/SN16KVAO datasheet, 24LC128T-E/SN16KVAO pinout, 24LC128T-E/SN16KVAO application, or 24LC128T-E/SN16KVAO equivalent, key selection criteria include VCC min (2.5V), page write time (≤5 ms), WP pin behavior, I²C bus timing compliance (THD:STA/TSU:STA), and SOIC-8 package mechanical compatibility.
Technical Context
The 24LC128T-E/SN16KVAO implements a two-wire I²C slave interface with Schmitt-trigger inputs on SDA/SCL for noise immunity and slope-controlled outputs to suppress ground bounce. Its internal address pointer supports sequential reads across the full 128Kbit memory space, while cascading up to eight devices via A0–A2 address pins enables scalable storage expansion.
Write operations are self-timed and internally managed: byte writes complete in ≤5 ms, and page writes (up to 64 bytes) use an on-chip latch to minimize host bus occupancy. The WP pin provides hardware-level protection of the entire memory array (0000h–3FFFh), sampled only at the Stop condition - ensuring robustness against accidental overwrites during power transitions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 128 Kbit (16,384 × 8) - supports firmware parameter storage, calibration tables, and event logs in resource-constrained systems. |
| VCC operating range | 2.5V to 5.5V - compatible with 3.3V and 5V logic domains without level shifting. |
| Max clock frequency | 400 kHz - enables ~3.2 kbyte/s sustained write throughput using page mode. |
| Page write buffer | 64 bytes - reduces I²C transaction overhead by batching writes; physical page boundaries align to 64-byte offsets. |
| Endurance & retention | 1 million erase/write cycles; >200 years data retention - suitable for long-life industrial deployments. |
| Standby current | ≤1 µA at I-temp - critical for battery-powered applications requiring multi-year operation. |
| Write-protect method | Hardware WP pin tied to VCC - prevents all writes regardless of I²C command sequence, including during brown-out. |
Pinout & Package
24LC128T-E/SN16KVAO uses an 8-lead SOIC (SN) package: 3.90 mm body width, 1.27 mm lead pitch, gull-wing leads. Pin 1 is top-left corner (A0), pin 8 is top-right (VCC). Package meets JEDEC MS-012AA standard.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0 | Chip address input | LSB of 3-bit slave address; hardwired to VSS/VCC to configure device address (000–111) on shared I²C bus. |
| A1 | Chip address input | Middle bit of slave address; enables up to eight 24LC128T-E/SN16KVAO devices on one bus (or two in MSOP). |
| A2 | Chip address input | MSB of slave address; determines unique I²C address (1010xx0/1) per device per bus segment. |
| VSS | Ground reference | Return path for all internal circuitry; must be low-impedance connection to system GND plane. |
| SDA | Serial data I/O | Open-drain bidirectional line; requires external pull-up (2–10 kΩ) to VCC; carries address, data, and ACK/NACK. |
| SCL | Serial clock input | Master-generated clock; rising edge samples data, falling edge allows data change; Schmitt-trigger input rejects noise. |
| WP | Write-protect control | Active-high enable: tied to VCC blocks all writes; tied to VSS enables full read/write access. |
| VCC | Power supply | 2.5–5.5V supply; decoupling capacitor (0.1 µF ceramic) required within 5 mm of pin for stable operation. |
Key Features
| Feature | Design Value |
|---|---|
| 64-byte page write buffer | Reduces I²C bus transactions by 64× vs. byte writes - cuts firmware execution time and bus contention in multi-device systems. |
| Schmitt-trigger inputs (SDA/SCL) | Provides ≥50 mV hysteresis (VHYS = 0.05×VCC) - eliminates false triggering from EMI or slow-rising signals in noisy industrial environments. |
| Self-timed write cycle | Internal erase/write completes in ≤5 ms without host polling delay - simplifies firmware and improves system responsiveness. |
| Hardware write-protection (WP) | Physically disables all write commands when WP = VCC - prevents corruption during power-up/down or software faults. |
| I²C bus compatibility | Fully compliant with standard-mode (100 kHz) and fast-mode (400 kHz) I²C specifications - interoperable with MCU peripherals and Linux I²C drivers. |
Applications
| Industrial Sensor Calibration | Medical Device Configuration |
|---|---|
|
Use Scenario: Storing factory-calibrated offset/gain coefficients for analog sensor front-ends in programmable logic controllers. IC Role / Device Role / Timing Role: Nonvolatile configuration storage accessed at boot; I²C read occurs once per power cycle; no runtime writes. Use Value: Ensures measurement accuracy across temperature and lifetime; 200-year retention guarantees calibration integrity over equipment service life. |
Use Scenario: Holding user-selectable therapy parameters (e.g., dose limits, alarm thresholds) in portable infusion pumps. IC Role / Device Role / Timing Role: Secure parameter store updated infrequently via microcontroller; WP pin grounded during normal operation. Use Value: Hardware write-protection prevents accidental or malicious parameter changes; 1M-cycle endurance supports field updates over 5+ years. |
| Automotive Body Control Module | Smart Energy Metering |
|
Use Scenario: Recording door lock actuation history and seat position memory in 12V automotive ECUs. IC Role / Device Role / Timing Role: Low-voltage EEPROM (2.5V min) surviving cold-crank conditions; accessed via I²C during wake-up sequences. Use Value: 2.5V operation ensures reliable boot-time reads during battery dips; AEC-Q100 qualification confirms automotive-grade reliability. |
Use Scenario: Logging tariff schedules, tamper events, and meter firmware version in ANSI C12.22-compliant electricity meters. IC Role / Device Role / Timing Role: High-endurance data logger writing timestamped records every 15 minutes; page writes optimize bus efficiency. Use Value: 64-byte page buffer reduces I²C traffic by 98% vs. byte writes - extends microcontroller sleep time and lowers system power. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 24AA128T-I/SN | Lower VCC min (1.7V), same 400 kHz max, identical SOIC-8 package and pinout. | Better suited for 1.8V/2.5V systems; not qualified for extended temp range. | Select when operating below 2.5V or needing wider voltage margin; verify WP behavior matches design. |
| AT24C128-10PU-2.7 | Same 128Kbit capacity, 1 MHz max clock, but requires ≥2.7V VCC; different I²C timing specs (e.g., THD:STA = 600 ns @ 2.7V). | Higher speed option for 3.3V systems; lacks AEC-Q100 qualification. | Choose for faster bus throughput in non-automotive designs; validate timing margins with host controller. |
Compared with 24LC128T-E/SN16KVAO, the 24AA128T-I/SN offers lower-voltage operation at the cost of automotive qualification, while the AT24C128-10PU-2.7 trades qualification for higher clock rate - making each alternative optimal only under specific voltage, speed, or compliance constraints.
Availability
24LC128T-E/SN16KVAO is available at Aetrix Electronics and suitable for industrial sensor calibration, medical device configuration, automotive body control modules, and smart energy metering requiring stable component supply across multi-year production cycles.
Supply support for 24LC128T-E/SN16KVAO includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog components, and memory solutions, headquartered in Chandler, Arizona, with global design and manufacturing operations.
The 24LC128T-E/SN16KVAO belongs to Microchip's 24XX128 family of I²C EEPROMs, engineered for robust, low-power nonvolatile storage in industrial, automotive, and medical applications where data integrity and long-term reliability are critical.
FAQ
What is the minimum supply voltage required for reliable operation of the 24LC128T-E/SN16KVAO?
The 24LC128T-E/SN16KVAO requires a minimum VCC of 2.5V for guaranteed operation across its full industrial temperature range (–40°C to +85°C). Below 2.5V, functionality is not specified - unlike the 24AA128 variant, which supports down to 1.7V. This makes the 24LC128T-E/SN16KVAO ideal for 3.3V and 5V systems but unsuitable for sub-2.5V battery-powered designs.
How does the WP pin function on the 24LC128T-E/SN16KVAO during power-up sequences?
The WP pin on the 24LC128T-E/SN16KVAO is sampled only at the Stop condition of each write command - not continuously. During power-up, if WP is held high (VCC), all subsequent write attempts will be ignored (though the device still acknowledges the command), preventing unintended writes during voltage ramp-up. This behavior ensures data safety even with uncontrolled power sequencing.
Can the 24LC128T-E/SN16KVAO perform sequential reads across the entire 128Kbit memory space?
Yes, the 24LC128T-E/SN16KVAO supports true sequential reads across its full address range (0000h–3FFFh). After the first byte is read, the internal address pointer auto-increments, allowing uninterrupted streaming of up to 16,384 bytes in a single I²C transaction - with automatic rollover from 3FFFh back to 0000h upon reaching the end.
What is the maximum number of 24LC128T-E/SN16KVAO devices that can share one I²C bus?
Up to eight 24LC128T-E/SN16KVAO devices can be cascaded on a single I²C bus using the A0, A1, and A2 address pins to generate unique 3-bit chip select codes (000–111). Each device responds only to its assigned slave address (1010xx0 for writes, 1010xx1 for reads), enabling scalable storage expansion without additional address decoding logic.
Does the 24LC128T-E/SN16KVAO support 1 MHz I²C clock frequency?
No, the 24LC128T-E/SN16KVAO is rated for a maximum clock frequency of 400 kHz. Only the 24FC128 variant in the same family supports 1 MHz operation. Attempting 1 MHz communication with the 24LC128T-E/SN16KVAO may result in timing violations, failed ACKs, or corrupted data transfers - especially at lower VCC levels or elevated temperatures.
24LC128T-E/SN16KVAO Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 128Kbit
- Memory Organization:
- 16K x 8
- Memory Interface:
- I2C
- Clock Frequency:
- 400 kHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- 900 ns
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
24LC128T-E/SN16KVAO FAQ
1.How can I place an order for 24LC128T-E/SN16KVAO through Aetrix?
Please submit a Request for Quotation (RFQ) for 24LC128T-E/SN16KVAO on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 24LC128T-E/SN16KVAO reliable?
The price and inventory of 24LC128T-E/SN16KVAO are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 24LC128T-E/SN16KVAO is usually 5 days.
3.What payment methods are accepted for 24LC128T-E/SN16KVAO?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 24LC128T-E/SN16KVAO transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 24LC128T-E/SN16KVAO?
24LC128T-E/SN16KVAO orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 24LC128T-E/SN16KVAO order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 24LC128T-E/SN16KVAO?
For technical support, including 24LC128T-E/SN16KVAO datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 24LC128T-E/SN16KVAO requirements.
6.How does Aetrix verify that 24LC128T-E/SN16KVAO is sourced from the original manufacturer or authorized distributors?
All 24LC128T-E/SN16KVAO products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 24LC128T-E/SN16KVAO meets industry standards.
7.What is the process for return or replacement of 24LC128T-E/SN16KVAO?
All 24LC128T-E/SN16KVAO units undergo pre-shipment inspection (PSI). If there is an issue with 24LC128T-E/SN16KVAO, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 24LC128T-E/SN16KVAO part is unused and in its original packaging.
Return procedure for 24LC128T-E/SN16KVAO:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
24LC128T-E/SN16KVAO Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

