Microchip Technology 24LCS22AT-I/SN
- Part No.:
- 24LCS22AT-I/SN
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
24LCS22AT-I/SN.pdf
- Description:
- IC EEPROM 2KBIT I2C 400KHZ 8SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
24LCS22AT-I/SN from Microchip Technology Inc. is a 2 Kbit dual-mode serial EEPROM designed for VESA DDC/EDID applications in display systems. It operates in Transmit-Only (1 Kbit) and Bidirectional (2 Kbit) modes, supports I²C™ at up to 400 kHz, features hardware write-protection via WP and VCLK pins, and delivers 1 mA active current with 10 μA standby current at 5.5V.
For engineers reviewing the 24LCS22AT-I/SN datasheet, 24LCS22AT-I/SN pinout, 24LCS22AT-I/SN application, or 24LCS22AT-I/SN equivalent, key selection criteria include dual-mode DDC1/DDC2 compatibility, E-EDID™ 1.3 support, flexible write-protect logic (WP + VCLK), 256 × 8-bit memory organization, and industrial-grade −40°C to +85°C operation in SOIC-8 package.
Technical Context
The 24LCS22AT-I/SN implements two independent serial protocols on shared SDA: VCLK-synchronized unidirectional transmission (DDC1™) and SCL-synchronized bidirectional I²C™ communication (DDC2™). Mode transition occurs only on valid high-to-low SCL edge, after which the device remains permanently in Bidirectional mode until power cycle.
Its internal architecture includes a Schmitt-triggered VCLK input for noise-immune DDC1 timing, programmable write-protection fuse (enabled by writing to address 7Fh), and page buffer supporting up to eight-byte writes. The device enforces strict bus timing per VESA DDC standards, including TVAA (2000 ns max output valid from VCLK) and TWR (10 ms max write cycle time).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 256 × 8-bit (2 Kbit), split into 1 Kbit Transmit-Only + full 2 Kbit Bidirectional access |
| Interface Modes | Transmit-Only (VCLK-clocked, DDC1™ compliant) and Bidirectional (SCL-clocked, I²C™-compatible) |
| Max Clock Frequency | 400 kHz at 4.5–5.5V; 100 kHz at 2.5–5.5V - defines maximum EDID read rate in monitor systems |
| Write Endurance | 1,000,000 erase/write cycles - ensures long-term reliability in firmware update or calibration storage |
| Data Retention | >200 years at 25°C - guarantees persistent EDID data across product lifetime without refresh |
| Supply Voltage Range | 2.5V to 5.5V - enables direct integration with 3.3V and 5V display controller rails |
| Operating Temperature | −40°C to +85°C (Industrial grade) - validated for use in commercial and industrial monitors |
| ESD Protection | >4000V HBM - safeguards against electrostatic discharge during board handling and system integration |
Pinout & Package
24LCS22AT-I/SN is housed in an 8-pin SOIC package (3.90 mm body width, SN suffix), RoHS-compliant and Pb-free. Pin 1 is marked with a beveled corner or dot; pins 1 and 8 are VSS and VCC respectively.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (VSS) | Ground reference | Common return path for all internal circuitry; must be low-impedance connection to system GND plane |
| 2 (VCLK) | Transmit-Only clock input / Write-enable control | Drives DDC1™ bitstream timing; must be held high to enable writes in Bidirectional mode |
| 3 (WP) | Hardware write-protect input | Active-low; enabled only after fuse set by writing to address 7Fh; provides dual-layer protection with VCLK |
| 4 (SDA) | Serial data I/O | Open-drain bidirectional line; requires external pull-up (2 kΩ for 400 kHz); shared between both modes |
| 5 (SCL) | Bidirectional clock input / Mode-select trigger | Initiates mode transition on high-to-low edge; controls I²C™ timing; must remain high to sustain Transmit-Only mode |
| 6 (NC) | No internal connection | Not bonded; must be left floating or tied to GND/VCC per layout best practice - no functional impact |
| 7 (NC) | No internal connection | Not bonded; same as Pin 6 - no routing required |
| 8 (VCC) | Power supply | Accepts 2.5–5.5V; decoupling capacitor (0.1 μF ceramic) required within 5 mm of pin |
Key Features
| Feature | Design Value |
|---|---|
| Fully compliant E-EDID™ 1.3 implementation | Enables plug-and-play display identification and resolution negotiation in modern PC and embedded video systems |
| Dual-mode architecture (Transmit-Only + Bidirectional) | Supports legacy DDC1™ monitors while enabling full I²C™-based configuration updates and diagnostics |
| Flexible hardware write protection (WP + VCLK) | Prevents accidental overwrites during system boot or hot-plug events; fuse-based lock adds tamper resistance |
| Self-timed write cycle with auto-erase | Eliminates need for external write timing control; 10 ms max duration ensures predictable firmware update latency |
| VESA DDC standard compliance with recovery logic | Guarantees interoperability with certified graphics controllers and avoids handshake failures in multi-monitor setups |
| Low-power CMOS design (1 mA active / 10 μA standby) | Minimizes power draw in always-on display subsystems and extends battery life in portable docking stations |
Applications
| Monitor EDID Storage | DisplayPort Sink Configuration |
|---|---|
Use Scenario: Storing Extended Display Identification Data (EDID) in LCD/LED monitors for automatic resolution and timing detection by host GPU. IC Role / Device Role / Timing Role: Primary nonvolatile memory for VESA-defined EDID block; transmits fixed 128-byte stream on VCLK in Transmit-Only mode during DDC1™ handshake. Use Value: Enables zero-configuration plug-and-play operation; eliminates manual display setup and ensures correct color depth/timing negotiation. | Use Scenario: Holding sink capability descriptors and link training parameters in DisplayPort-enabled monitors and projectors. IC Role / Device Role / Timing Role: I²C™ slave device providing dynamic configuration data to source during AUX channel communication; accessed via Bidirectional mode. Use Value: Supports adaptive link rate negotiation and multi-stream transport (MST) topology reporting without requiring FPGA or MCU intervention. |
| KVM Switch Firmware Table | Digital Signage Controller Calibration |
Use Scenario: Storing port mapping tables, EDID profiles, and user preferences in enterprise KVM switches supporting multiple video sources. IC Role / Device Role / Timing Role: Dual-role EEPROM: serves static EDID in Transmit-Only mode to connected displays, and stores dynamic routing config in Bidirectional mode. Use Value: Allows seamless switching between PCs with different native resolutions while preserving each display's optimal settings. | Use Scenario: Retaining gamma curves, white point offsets, and brightness calibration values across power cycles in commercial digital signage players. IC Role / Device Role / Timing Role: Nonvolatile parameter store accessed via I²C™ during boot; write-protected during normal operation using WP+VCLK logic. Use Value: Ensures consistent color reproduction and eliminates recalibration labor in deployed installations. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT24C02C-SSHM-T | Single-mode I²C™-only (no VCLK/Transmit-Only mode); 2 Kbit; 1 MHz max clock; no VCLK pin or DDC-specific timing | Lacks DDC1™ compatibility; cannot replace 24LCS22AT-I/SN in legacy monitor designs requiring VCLK-synchronized EDID broadcast | Select only if system uses pure I²C™-based configuration and does not require VESA DDC1™ compliance. |
| 24LC024T-I/SN | 2 Kbit I²C™ EEPROM with single write-protect pin; no VCLK pin; no Transmit-Only mode; identical SOIC-8 package and voltage range | Cannot emulate DDC1™ behavior; requires host MCU to manage EDID reads instead of autonomous VCLK-driven transmission | Choose when EDID is handled by application processor rather than direct hardware handshake with graphics controller. |
Compared with AT24C02C-SSHM-T and 24LC024T-I/SN, the 24LCS22AT-I/SN uniquely delivers VESA-certifiable DDC1™/DDC2™ dual-mode operation - essential for monitor ICs that must autonomously broadcast EDID without host intervention, while retaining field-upgradable configuration storage.
Availability
24LCS22AT-I/SN is available at Aetrix Electronics and suitable for display interface design, monitor manufacturing, and digital signage development requiring stable component supply, long-lifecycle assurance, and VESA-compliant EDID functionality.
Supply support for 24LCS22AT-I/SN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog components, and memory solutions, headquartered in Chandler, Arizona, with global design and manufacturing operations.
The 24LCS22AT-I/SN belongs to Microchip's VESA-qualified serial EEPROM product line, engineered specifically for reliable, standards-compliant EDID storage and DDC communication in display subsystems.
FAQ
What is the primary function of the VCLK pin on the 24LCS22AT-I/SN?
The VCLK pin on the 24LCS22AT-I/SN serves two critical roles: in Transmit-Only mode, it clocks out the EDID bitstream synchronously for DDC1™ compliance; in Bidirectional mode, it acts as a write-enable control - held high to permit writes, low to block them. This dual function is unique to the 24LCS22AT-I/SN and essential for VESA-standard monitor interfaces.
How does the 24LCS22AT-I/SN differ from standard I²C™ EEPROMs like the 24LC02B?
Unlike standard I²C™ EEPROMs such as the 24LC02B, the 24LCS22AT-I/SN integrates a dedicated VCLK input and dual-mode logic to natively support both DDC1™ (unidirectional, VCLK-driven) and DDC2™ (bidirectional, SCL-driven) protocols. It also includes VESA-specific timing parameters (e.g., TVAA, TVHIGH) and mode-transition recovery logic absent in generic EEPROMs.
Can the 24LCS22AT-I/SN be used in systems that only require I²C™ communication, without DDC functionality?
Yes - the 24LCS22AT-I/SN fully supports standard I²C™ read/write operations in Bidirectional mode using SCL/SDA, with slave address 1010000x. Its 2 Kbit memory, 400 kHz speed, and industrial temperature range make it suitable for general-purpose configuration storage, provided the VCLK pin is held high and WP is managed per application needs.
What happens if the SCL pin receives a spurious pulse during Transmit-Only mode operation?
A valid high-to-low transition on SCL forces the 24LCS22AT-I/SN into Transition mode and initiates a 128-VCLK pulse timeout window. If no matching I²C™ control byte (1010000x) is received before timeout, the device automatically reverts to Transmit-Only mode. This recovery mechanism prevents unintended mode lockup due to noise or glitches on SCL.
Is the write-protection feature of the 24LCS22AT-I/SN reversible after enabling the WP fuse?
No - once address 7Fh is written to set the write-protection fuse, the WP pin becomes active and cannot be disabled. The 24LCS22AT-I/SN then requires both VCLK = high AND WP = high for writes to proceed. This one-time fuse ensures permanent hardware-level protection of critical EDID or calibration data against accidental or malicious overwrite.
24LCS22AT-I/SN Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 2Kbit
- Memory Organization:
- 256 x 8
- Memory Interface:
- I2C
- Clock Frequency:
- 400 kHz
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- 900 ns
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
24LCS22AT-I/SN FAQ
1.How can I place an order for 24LCS22AT-I/SN through Aetrix?
Please submit a Request for Quotation (RFQ) for 24LCS22AT-I/SN on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 24LCS22AT-I/SN reliable?
The price and inventory of 24LCS22AT-I/SN are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 24LCS22AT-I/SN is usually 5 days.
3.What payment methods are accepted for 24LCS22AT-I/SN?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 24LCS22AT-I/SN transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 24LCS22AT-I/SN?
24LCS22AT-I/SN orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 24LCS22AT-I/SN order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 24LCS22AT-I/SN?
For technical support, including 24LCS22AT-I/SN datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 24LCS22AT-I/SN requirements.
6.How does Aetrix verify that 24LCS22AT-I/SN is sourced from the original manufacturer or authorized distributors?
All 24LCS22AT-I/SN products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 24LCS22AT-I/SN meets industry standards.
7.What is the process for return or replacement of 24LCS22AT-I/SN?
All 24LCS22AT-I/SN units undergo pre-shipment inspection (PSI). If there is an issue with 24LCS22AT-I/SN, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 24LCS22AT-I/SN part is unused and in its original packaging.
Return procedure for 24LCS22AT-I/SN:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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