Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Memory > Memory

Microchip Technology 25AA010AT-I/SN

Name: 25AA010AT-I/SN
Brand: Microchip Technology
SKU: 25AA010AT-I/SN
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: 25AA010AT-I/SN

Manufacturer:: Microchip Technology

Category:: Memory

Package:: 8-SOIC (0.154", 3.90mm Width)

Datasheet:: 25AA010AT-I/SN.pdf

Description:: IC EEPROM 1KBIT SPI 10MHZ 8SOIC

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:7,575

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

25AA010AT-I/SN from Microchip Technology is a 1 Kbit (128 × 8) SPI serial EEPROM with 1.8–5.5 V supply, 10 MHz max clock frequency, 16-byte page write capability, and industrial temperature range (−40°C to +85°C). It features hardware write protection (WP pin), HOLD functionality for interrupt-safe bus suspension, and block-level write protection (none/¼/½/all array). Used in microcontroller-based systems for storing calibration data, configuration settings, or firmware patches.

For engineers reviewing the 25AA010AT-I/SN datasheet, 25AA010AT-I/SN pinout, 25AA010AT-I/SN application, or 25AA010AT-I/SN equivalent, key selection criteria include SPI timing compatibility at 1.8 V, WP/HOLD pin behavior under system interrupt conditions, endurance (1M cycles) vs. retention (>200 years), and SOIC-8 (SN) package footprint constraints in space-constrained designs.

Technical Context

The 25AA010AT-I/SN implements a standard SPI Mode 0,0 (CPOL=0, CPHA=0) interface with separate SI (data in) and SO (data out) lines, requiring CS, SCK, SI, SO, WP, HOLD, VCC, and VSS. It uses an internal high-voltage generator for EEPROM programming and includes a nonvolatile STATUS register with WIP, WEL, BP0, and BP1 bits for real-time write status and configurable block protection.

Write operations require explicit WREN instruction followed by CS high-to-low transition to initiate self-timed internal write cycle (≤5 ms); page writes are bounded to 16-byte physical pages (e.g., addresses 00h–0Fh, 10h–1Fh), with wraparound on boundary violation. HOLD suspends ongoing transfers while preserving internal state, enabling host MCU to service higher-priority interrupts without reinitializing the SPI sequence.

Key Specifications

Parameter	Value and Actual Design Meaning
Memory Size	1 Kbit (128 × 8-bit array), sufficient for small configuration tables or device ID storage in resource-limited MCUs.
Interface	SPI-compatible serial bus (Mode 0,0), compatible with PIC® and most ARM Cortex-M microcontrollers' hardware SPI peripherals.
Max Clock Frequency	10 MHz at VCC ≥ 4.5 V, enabling fast read/write throughput (up to ~1.25 MB/s theoretical burst read).
Write Cycle Time	≤5 ms per byte or page, deterministic timing critical for real-time systems needing predictable nonvolatile write latency.
Endurance & Retention	1,000,000 erase/write cycles and >200 years data retention at 25°C, validated for long-life industrial deployments.
Supply Voltage Range	1.8–5.5 V, supporting direct interfacing with 1.8 V, 3.3 V, and 5 V logic domains without level shifters.
Operating Temperature	−40°C to +85°C (Industrial grade), qualified for use in automotive body control modules and industrial sensors.

Pinout & Package

25AA010AT-I/SN is packaged in 8-lead SOIC (SN), with 1.27 mm pitch, 4.9 mm × 3.9 mm body size, and Pb-free/RoHS-compliant finish.

Pin/Terminal	Circuit Role	Design Meaning
1 - CS	Chip Select Input	Active-low enable; must be low for all SPI transactions; rising edge initiates internal write cycle after valid write sequence.
2 - SO	Serial Data Output	Tri-state open-drain output; delivers read data MSb-first on falling edge of SCK; high-impedance when CS high or during HOLD.
3 - WP	Write-Protect Pin	Hardware lock: low disables all writes (array and STATUS register); overrides WEL bit; retains protection during power transitions.
4 - VSS	Ground	Reference return path for all digital and analog circuitry; must be low-impedance connection to minimize noise coupling into EEPROM core.
5 - SI	Serial Data Input	CMOS input latching instruction/address/data on rising edge of SCK; requires clean signal integrity to avoid spurious command execution.
6 - SCK	Serial Clock Input	Master-generated clock; defines timing for SI sampling (rising edge) and SO update (falling edge); max 10 MHz at 4.5–5.5 V.
7 - HOLD	Hold Input	Active-low pause: suspends ongoing SPI transfer without resetting state; must be asserted only when SCK is low to avoid metastability.
8 - VCC	Supply Voltage	1.8–5.5 V power rail; internal voltage regulator enables stable operation across full range; decoupling capacitor required near pin.

Key Features

Feature	Design Value
Page Write Mode	Up to 16 bytes written per internal cycle, reducing total write time vs. byte-by-byte writes-critical for logging burst sensor data.
Block Write Protection	Selectable via STATUS register (BP0/BP1): protects none, upper 1/4 (60h–7Fh), upper 1/2 (40h–7Fh), or entire array (00h–7Fh) against accidental overwrite.
Built-in Power-On Protection	Write enable latch resets at power-up; WP pin active low by default; prevents corruption during brown-out or reset sequences.
HOLD Functionality	Pauses SPI communication mid-sequence without losing address pointer or command state-enables deterministic interrupt handling in real-time OS environments.
Low-Power Operation	Standby current ≤5 µA at 5.5 V/125°C; read/write current ≤5 mA at 5.5 V/10 MHz-suitable for battery-backed or energy-harvesting applications.

Applications

Industrial Sensor Calibration	Medical Device Configuration
Use Scenario: Storing factory-calibrated offset/gain coefficients for analog front-end circuits in pressure or temperature transmitters. IC Role / Device Role / Timing Role: Nonvolatile parameter storage accessed at boot; SPI read occurs once per power cycle with no timing constraints. Use Value: Eliminates need for external calibration trimmers; enables field recalibration via firmware update while preserving traceability data across 200+ year retention.	Use Scenario: Holding user-selectable therapy parameters (e.g., dose rate, alarm thresholds) in portable insulin pumps or infusion controllers. IC Role / Device Role / Timing Role: Secure configuration store with hardware WP pin permanently tied low during normal operation to prevent runtime corruption. Use Value: Meets IEC 62304 safety requirements for writable memory; 1M-cycle endurance supports >10 years of daily parameter adjustments.
Automotive Body Control Module	Smart Energy Meter Firmware Patch
Use Scenario: Storing seat position memory, mirror angle presets, or lighting profiles in 12 V automotive cabin ECUs. IC Role / Device Role / Timing Role: SPI EEPROM interfaced directly to 3.3 V MCU; HOLD pin used to pause writes during CAN bus interrupt servicing. Use Value: −40°C to +85°C rating ensures reliability across vehicle thermal cycling; SOIC-8 (SN) footprint fits tight PCB layouts near MCU.	Use Scenario: Hosting field-upgradable bootloader patches or tariff schedule updates in utility-grade electricity meters with 15+ year service life. IC Role / Device Role / Timing Role: Stores signed firmware fragments; write verification via RDSR polling (WIP bit) ensures atomic update completion before power loss. Use Value: >200-year data retention guarantees meter accuracy over full product lifecycle; 1.8 V min operation supports supercapacitor backup during mains outage.

Industrial Sensor Calibration

Medical Device Configuration

Use Scenario: Storing factory-calibrated offset/gain coefficients for analog front-end circuits in pressure or temperature transmitters.

IC Role / Device Role / Timing Role: Nonvolatile parameter storage accessed at boot; SPI read occurs once per power cycle with no timing constraints.

Use Value: Eliminates need for external calibration trimmers; enables field recalibration via firmware update while preserving traceability data across 200+ year retention.

Use Scenario: Holding user-selectable therapy parameters (e.g., dose rate, alarm thresholds) in portable insulin pumps or infusion controllers.

IC Role / Device Role / Timing Role: Secure configuration store with hardware WP pin permanently tied low during normal operation to prevent runtime corruption.

Use Value: Meets IEC 62304 safety requirements for writable memory; 1M-cycle endurance supports >10 years of daily parameter adjustments.

Automotive Body Control Module

Smart Energy Meter Firmware Patch

Use Scenario: Storing seat position memory, mirror angle presets, or lighting profiles in 12 V automotive cabin ECUs.

IC Role / Device Role / Timing Role: SPI EEPROM interfaced directly to 3.3 V MCU; HOLD pin used to pause writes during CAN bus interrupt servicing.

Use Value: −40°C to +85°C rating ensures reliability across vehicle thermal cycling; SOIC-8 (SN) footprint fits tight PCB layouts near MCU.

Use Scenario: Hosting field-upgradable bootloader patches or tariff schedule updates in utility-grade electricity meters with 15+ year service life.

IC Role / Device Role / Timing Role: Stores signed firmware fragments; write verification via RDSR polling (WIP bit) ensures atomic update completion before power loss.

Use Value: >200-year data retention guarantees meter accuracy over full product lifecycle; 1.8 V min operation supports supercapacitor backup during mains outage.

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial EEPROM applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
25LC010AT-I/SN	Requires 2.5–5.5 V supply; lacks 1.8 V operation; otherwise identical pinout, timing, and feature set.	Not suitable for 1.8 V systems (e.g., ultra-low-power IoT nodes); acceptable where 3.3 V or 5 V rails dominate.	Select only if system VCC never drops below 2.5 V; verify timing margins at 2.5 V per Table 1-2 AC specs.
AT25010B-SSHL-T	Same 1 Kbit SPI EEPROM but with 20 MHz max clock (at 2.7–5.5 V); different STATUS register layout and WP behavior (active-high).	Higher-speed read bursts possible; requires firmware adaptation for STATUS bit mapping and WP polarity inversion.	Choose for bandwidth-critical applications; validate hold-time and setup-time compliance with host MCU's SPI peripheral at target VCC.

Compared with 25AA010AT-I/SN, the 25LC010AT-I/SN trades 1.8 V compatibility for identical industrial-grade reliability, while the AT25010B-SSHL-T offers higher speed but demands firmware changes for status polling and write-protection logic-making 25AA010AT-I/SN optimal for cost-sensitive, low-voltage, drop-in legacy replacements.

Availability

25AA010AT-I/SN is available at Aetrix Electronics and suitable for industrial sensor calibration, medical device configuration, and automotive body control modules requiring stable component supply across extended product lifecycles.

Supply support for 25AA010AT-I/SN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology Inc. is a leading provider of microcontrollers, analog components, and memory solutions, headquartered in Chandler, Arizona, with global design and manufacturing operations.

The 25AA010A family was designed specifically for reliable, low-power, SPI-based nonvolatile storage in cost-sensitive embedded systems-emphasizing robustness across voltage and temperature extremes while maintaining strict SPI protocol compliance.

FAQ

What is the minimum supply voltage supported by the 25AA010AT-I/SN?

The 25AA010AT-I/SN operates down to 1.8 V, enabling direct integration with 1.8 V logic families and ultra-low-power microcontrollers without level-shifting circuitry. This is confirmed in the Device Selection Table and DC Characteristics section (D010–D012) of DS21832H, where read/write/standby currents are specified at 1.8 V, 2.5 V, and 5.5 V.

Does the 25AA010AT-I/SN support page write operations, and what is the maximum page size?

Yes, the 25AA010AT-I/SN supports page write mode with a fixed 16-byte page size, as stated in the Features list and Section 2.3. Each page spans contiguous addresses (e.g., 00h–0Fh), and attempting to cross a page boundary wraps data to the start of the same page-requiring firmware to align writes to page boundaries for predictable behavior.

How does the HOLD pin function during an active SPI transaction on the 25AA010AT-I/SN?

The HOLD pin on the 25AA010AT-I/SN pauses ongoing SPI communication while preserving internal state (address pointer, command context). It must be driven low while SCK is low; doing so places SI, SCK, and SO in high-impedance states. Resuming requires bringing HOLD high while SCK remains low-ensuring deterministic interrupt handling without retransmission overhead.

What protection mechanisms prevent unintended writes to the 25AA010AT-I/SN memory array?

The 25AA010AT-I/SN employs three layered protections: (1) a volatile write-enable latch (WEL) that resets on power-up or WRDI; (2) a hardware WP pin that disables all writes when low; and (3) nonvolatile block protection bits (BP0/BP1) in the STATUS register. All are detailed in Sections 2.4, 2.7, and Table 2-4 of DS21832H.

Is the 25AA010AT-I/SN pin-compatible with other Microchip 1 Kbit SPI EEPROMs like the 25LC010A?

Yes, the 25AA010AT-I/SN shares identical pinout, package (SOIC-8 SN), and SPI interface timing with the 25LC010A series. However, it differs electrically: 25AA010AT-I/SN supports 1.8–5.5 V operation, while 25LC010A requires 2.5–5.5 V. Both use the same instruction set and STATUS register format, enabling direct substitution where voltage range permits.

25AA010AT-I/SN Specifications

Product attributes: Attribute value

Manufacturer:: Microchip Technology

Series:: -

Package/Case:: 8-SOIC (0.154", 3.90mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Verified

Memory Type:: Non-Volatile

Memory Format:: EEPROM

Technology:: EEPROM

Memory Size:: 1Kbit

Memory Organization:: 128 x 8

Memory Interface:: SPI

Clock Frequency:: 10 MHz

Write Cycle Time - Word, Page:: 5ms

Access Time:: -

Voltage - Supply:: 1.8V ~ 5.5V

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 8-SOIC

25AA010AT-I/SN FAQ

1.How can I place an order for 25AA010AT-I/SN through Aetrix?

Please submit a Request for Quotation (RFQ) for 25AA010AT-I/SN on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 25AA010AT-I/SN reliable?

The price and inventory of 25AA010AT-I/SN are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 25AA010AT-I/SN is usually 5 days.

3.What payment methods are accepted for 25AA010AT-I/SN?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 25AA010AT-I/SN transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 25AA010AT-I/SN?

25AA010AT-I/SN orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 25AA010AT-I/SN order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 25AA010AT-I/SN?

For technical support, including 25AA010AT-I/SN datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 25AA010AT-I/SN requirements.

6.How does Aetrix verify that 25AA010AT-I/SN is sourced from the original manufacturer or authorized distributors?

All 25AA010AT-I/SN products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 25AA010AT-I/SN meets industry standards.

7.What is the process for return or replacement of 25AA010AT-I/SN?

All 25AA010AT-I/SN units undergo pre-shipment inspection (PSI). If there is an issue with 25AA010AT-I/SN, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 25AA010AT-I/SN part is unused and in its original packaging.

Return procedure for 25AA010AT-I/SN:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…