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Microchip Technology 25AA128-I/ST
- Part No.:
- 25AA128-I/ST
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
25AA128-I/ST.pdf
- Description:
- IC EEPROM 128KBIT SPI 8TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:4,884
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Product details
Overview
25AA128-I/ST from Microchip Technology Inc. is a 128 Kbit SPI Serial EEPROM with 16,384 × 8-bit organization, 64-byte page size, and industrial temperature range (–40°C to +85°C). It operates from 1.8V to 5.5V, supports up to 10 MHz clock at 4.5–5.5V, and delivers 5 µA standby current. It is used for nonvolatile parameter storage in microcontroller-based systems requiring robust data retention and hardware write protection.
For engineers reviewing the 25AA128-I/ST datasheet, 25AA128-I/ST pinout, 25AA128-I/ST application, or 25AA128-I/ST equivalent, this page provides verified electrical specs, SPI timing constraints, HOLD/CS/WP functional behavior, package-specific pin mapping for TSSOP-8, and real-world use cases in embedded control, sensor calibration, and configuration memory.
Technical Context
The 25AA128-I/ST implements a standard SPI Mode 0,0 interface with separate SI (data in) and SO (data out) lines, requiring CS low for selection and SCK for synchronization. Its internal architecture includes a write-enable latch, STATUS register with WIP/WEL/BP0/BP1 bits, and hardware write-protection controlled by WP pin and WPEN bit.
It supports byte and page writes (up to 64 bytes within one 64-byte page boundary), self-timed internal write cycles (≤5 ms), and sequential read with automatic address increment. The HOLD pin suspends ongoing SPI transfers without resetting the sequence, enabling interrupt servicing while preserving bus state.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 128 Kbit (16,384 × 8-bit), sufficient for firmware configuration, calibration tables, or device ID storage in resource-constrained systems. |
| Interface | SPI-compatible serial bus (Mode 0,0), compatible with PIC® and most MCU SPI peripherals without bit-banging overhead. |
| Max Clock Frequency | 10 MHz at VCC ≥ 4.5V - enables fast read/write throughput (e.g., ~1.28 MB/s theoretical read rate) in high-speed host systems. |
| Page Size | 64 bytes - defines maximum contiguous write length; crossing page boundaries wraps data, requiring software boundary checks. |
| Write Endurance | 1,000,000 erase/write cycles - supports frequent field updates (e.g., logging, counters) over product lifetime. |
| Data Retention | >200 years at 25°C - ensures long-term reliability of stored settings without refresh in battery-backed or maintenance-free applications. |
| Supply Voltage Range | 1.8V to 5.5V - allows direct interfacing with 1.8V, 3.3V, and 5V logic domains without level shifters. |
| Standby Current | 5 µA at 5.5V and 125°C - critical for ultra-low-power applications such as IoT edge nodes operating on coin cells. |
Pinout & Package
25AA128-I/ST is packaged in an 8-Lead TSSOP (Thin Shrink Small Outline Package) with 0.65 mm pitch, JEDEC MO-153 compliant, and marked "25AA128-I/ST" with date code and traceability. Pin 1 is located at the top-left corner (notch-marked side).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (CS) | Chip Select Input | Active-low enable; must be low for all SPI operations; rising edge initiates internal write cycle after valid write sequence. |
| 2 (SO) | Serial Data Output | Tri-state open-drain output; data shifts out MSB-first on falling SCK edge; goes high-Z when CS high or HOLD active. |
| 3 (WP) | Write-Protect Input | Hardware lock for STATUS register when WPEN=1; low = blocks nonvolatile STATUS writes; high = full access. |
| 4 (VSS) | Ground | Reference return path for all I/O and core logic; must be low-impedance connection to system ground plane. |
| 5 (SI) | Serial Data Input | CMOS input; latches instruction/address/data on rising SCK edge; requires setup/hold timing per AC specs (e.g., TSU=10 ns @ 5V). |
| 6 (SCK) | Serial Clock Input | Master-generated clock; defines SPI timing window; rise/fall times ≤100 ns required for 10 MHz operation. |
| 7 (HOLD) | Hold Input | Active-low pause signal; must be asserted while SCK is low; suspends SPI transfer without losing internal state or address pointer. |
| 8 (VCC) | Supply Voltage | Power input (1.8–5.5V); decoupling capacitor (0.1 µF ceramic) required within 5 mm of pin for noise immunity and stable write cycles. |
Key Features
| Feature | Design Value |
|---|---|
| Block Write Protection | Configurable via BP0/BP1 bits: protect none, upper 1/4 (3000h–3FFFh), upper 1/2 (2000h–3FFFh), or entire array (0000h–3FFFh). |
| Hardware Write Protection | WP pin + WPEN bit enable/disable nonvolatile STATUS register writes - prevents accidental corruption of protection settings in field-deployed units. |
| Self-Timed Write Cycle | Internal 5 ms max write completion; eliminates need for host polling delay - simplifies firmware and improves deterministic timing. |
| HOLD Functionality | Pauses active SPI transaction mid-sequence; preserves address pointer and command state - enables real-time interrupt handling without retransmission. |
| Power-On Safety | Write enable latch resets at power-up; SO defaults to high-Z; CS must go low before first operation - prevents spurious writes during supply ramp. |
| High Reliability | 1M endurance cycles and >200-year data retention validated per JEDEC standards - suitable for mission-critical storage in industrial controllers. |
Applications
| Industrial Sensor Calibration | Medical Device Configuration |
|---|---|
|
Use Scenario: Storing factory-calibrated offset/gain coefficients and linearization tables for analog sensor front-ends in programmable logic controllers. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed at boot and during recalibration routines via SPI from host MCU. Use Value: Enables field-upgradable calibration without firmware reflashing; 64-byte page writes allow atomic update of multi-parameter sets. |
Use Scenario: Holding user-selectable therapy parameters, device serial number, and usage logs in portable infusion pumps. IC Role / Device Role / Timing Role: Secure, low-power parameter store with hardware write protection to prevent unauthorized modification of safety-critical settings. Use Value: WP pin + WPEN bit ensures tamper-resistant storage; 5 µA standby current extends battery life between charges. |
| Automotive ECU Boot Settings | Smart Meter Firmware Metadata |
|
Use Scenario: Saving adaptive learning values (e.g., idle air control trim, fuel trims) across ignition cycles in engine control modules. IC Role / Device Role / Timing Role: AEC-Q100 qualified EEPROM interfacing directly with automotive-grade MCU SPI peripheral under wide temperature and voltage variation. Use Value: Industrial temp grade (–40°C to +85°C) and 1.8V operation support cold-cranking and stop-start conditions without data loss. |
Use Scenario: Recording firmware version, upgrade timestamp, cryptographic keys, and metering history in utility smart meters deployed for 15+ years. IC Role / Device Role / Timing Role: Long-life nonvolatile memory storing immutable metadata and security credentials accessible only via authenticated host commands. Use Value: >200-year data retention and 1M endurance guarantee integrity of regulatory-compliant records over full product lifecycle. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 25LC128-I/ST | Requires VCC ≥ 2.5V; identical pinout, timing, and feature set but narrower voltage range. | Not suitable for 1.8V systems; otherwise drop-in replacement where supply rails are stable ≥2.5V. | Select when system VCC is guaranteed ≥2.5V and cost optimization is prioritized over 1.8V compatibility. |
| AT25128B-SSHL-T | Same 128 Kbit SPI EEPROM, but uses different STATUS register layout and lacks HOLD pin; max clock 20 MHz at 5V. | No HOLD functionality limits interrupt-safe operation; higher clock supports faster bulk reads but requires updated driver timing. | Choose when HOLD is unused and higher throughput justifies redesigning SPI transaction handling and verifying STATUS register compatibility. |
Compared with 25LC128-I/ST, the 25AA128-I/ST adds 1.8V operation for ultra-low-voltage designs; compared with AT25128B-SSHL-T, it retains HOLD for deterministic interrupt response and maintains Microchip's proven write-protection matrix - making it optimal for safety-aware, mixed-voltage embedded systems.
Availability
25AA128-I/ST is available at Aetrix Electronics and suitable for industrial automation, medical instrumentation, and automotive electronics requiring stable component supply, long-lifecycle support, and RoHS-compliant packaging.
Supply support for 25AA128-I/ST includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog devices, and memory solutions, headquartered in Chandler, Arizona, with global design and manufacturing operations.
The 25AA128-I/ST belongs to Microchip's 25XX128 family of SPI EEPROMs, designed specifically for reliable, low-power, pin-efficient nonvolatile storage in space-constrained embedded systems across industrial, medical, and automotive markets.
FAQ
What is the minimum supply voltage for reliable operation of the 25AA128-I/ST?
The 25AA128-I/ST operates reliably from 1.8V to 5.5V. At 1.8V, maximum clock frequency is reduced to 3 MHz per AC specifications, and read/write currents scale accordingly. All features-including HOLD, WP, and STATUS register access-remain fully functional across this range, making the 25AA128-I/ST suitable for battery-powered or energy-harvesting systems where rail voltage varies.
Does the 25AA128-I/ST support SPI Mode 1,1 or other clock polarity/phase variants?
No, the 25AA128-I/ST is strictly compliant with SPI Mode 0,0 (CPOL = 0, CPHA = 0): clock idles low, data sampled on rising edge, and output changes on falling edge. Attempting Mode 1,1 or other variants will result in communication failure. Host firmware must configure its SPI peripheral accordingly; no mode-switching capability exists within the 25AA128-I/ST.
How does the HOLD pin behave during an active write cycle?
The HOLD pin has no effect on an ongoing internal write cycle (TWC). Once CS rises after a valid write sequence, the 25AA128-I/ST begins its self-timed 5 ms write operation, during which HOLD assertions are ignored. HOLD only pauses active SPI transactions - not internal writes - so host software must poll the WIP bit in the STATUS register to determine write completion.
Can the 25AA128-I/ST be used in AEC-Q100 qualified automotive applications?
Yes - the 25AA128-I/ST carries AEC-Q100 qualification for Grade 3 (–40°C to +85°C), confirming reliability under automotive thermal, vibration, and ESD stress conditions. Its 4 kV HBM ESD rating, 1M endurance, and >200-year data retention meet stringent automotive requirements for ECUs, body control modules, and ADAS subsystems where firmware metadata or calibration data must survive vehicle lifetime.
What happens if a page write crosses a 64-byte boundary on the 25AA128-I/ST?
If a page write command attempts to write across a 64-byte boundary (e.g., starting at address 0x003F and writing 4 bytes), the 25AA128-I/ST wraps the data to the start of the same page (0x0000), overwriting prior contents. This behavior is documented and deterministic - application firmware must enforce page alignment or split multi-page writes explicitly to avoid unintended data corruption.
25AA128-I/ST Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 128Kbit
- Memory Organization:
- 16K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 10 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
25AA128-I/ST FAQ
1.How can I place an order for 25AA128-I/ST through Aetrix?
Please submit a Request for Quotation (RFQ) for 25AA128-I/ST on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 25AA128-I/ST reliable?
The price and inventory of 25AA128-I/ST are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 25AA128-I/ST is usually 5 days.
3.What payment methods are accepted for 25AA128-I/ST?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 25AA128-I/ST transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 25AA128-I/ST?
25AA128-I/ST orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 25AA128-I/ST order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 25AA128-I/ST?
For technical support, including 25AA128-I/ST datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 25AA128-I/ST requirements.
6.How does Aetrix verify that 25AA128-I/ST is sourced from the original manufacturer or authorized distributors?
All 25AA128-I/ST products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 25AA128-I/ST meets industry standards.
7.What is the process for return or replacement of 25AA128-I/ST?
All 25AA128-I/ST units undergo pre-shipment inspection (PSI). If there is an issue with 25AA128-I/ST, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 25AA128-I/ST part is unused and in its original packaging.
Return procedure for 25AA128-I/ST:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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