Microchip Technology 25LC010A-E/P
- Part No.:
- 25LC010A-E/P
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-DIP (0.300", 7.62mm)
- Datasheet:
-
25LC010A-E/P.pdf
- Description:
- IC EEPROM 1KBIT SPI 10MHZ 8DIP
- Quantity:
- Payment:

- Shipping:

Inventory:2,697
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
25LC010A-E/P from Microchip Technology Inc. is a 1 Kbit (128 × 8) SPI Serial EEPROM with 16-byte page write capability, 10 MHz max clock frequency, and automotive-grade temperature support (−40°C to +125°C). It features hardware write protection (WP pin), HOLD functionality for interrupt-safe serial communication, and block-level array protection (none/¼/½/all). Used in engine control units, ADAS sensor modules, and automotive infotainment for nonvolatile parameter storage.
For engineers reviewing the 25LC010A-E/P datasheet, 25LC010A-E/P pinout, 25LC010A-E/P application, or 25LC010A-E/P equivalent, key selection criteria include VCC range (2.5–5.5 V), endurance (1 million cycles), data retention (>200 years), SPI timing compliance (Mode 0,0 and 1,1), and automotive qualification per E-temp grade.
Technical Context
The 25LC010A-E/P implements a standard SPI interface with separate SI (data in), SO (data out), SCK (clock), CS (chip select), WP (write-protect), and HOLD (pause) signals. It uses an internal 8-bit instruction register and supports MSb-first transmission of READ/WRITE/RDSR/WRSR commands.
Write operations require explicit WREN instruction and CS high transition to initiate self-timed internal write cycle (≤5 ms). Block protection is controlled via BP0/BP1 bits in the STATUS register, enabling selective write-locking of memory segments - critical for firmware configuration safety in automotive systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 1 Kbit (128 × 8-bit organization), sufficient for calibration tables, device IDs, and fault logs in compact ECUs. |
| Interface | SPI-compatible serial bus (Mode 0,0 and Mode 1,1), compatible with PIC® and ARM-based microcontrollers without custom GPIO bit-banging. |
| Max Clock Frequency | 10 MHz at VCC ≥ 4.5 V, enabling fast parameter reads during boot or diagnostics without CPU bus contention. |
| Write Cycle Time | ≤5 ms per byte or page, deterministic timing for real-time system recovery after power loss or reset. |
| Endurance & Retention | 1,000,000 erase/write cycles and >200 years data retention at 25°C - validated for lifetime operation in automotive underhood environments. |
| Supply Voltage | 2.5 V to 5.5 V, supporting direct connection to 3.3 V or 5 V MCU I/O rails without level-shifting circuitry. |
| Temperature Range | −40°C to +125°C (Automotive E-grade), qualified for placement near powertrain or chassis control electronics. |
Pinout & Package
25LC010A-E/P is supplied in 8-lead PDIP (Plastic Dual In-line Package) with lead finish Matte Tin (Pb-free, RoHS compliant). Pin 1 is marked by laser dot; package outline conforms to JEDEC MS-001.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS (Pin 1) | Chip Select Input | Active-low enable: drives device into active mode; rising edge initiates internal write cycle after valid WRITE sequence. |
| SO (Pin 2) | Serial Data Output | Tri-state output: shifts out read data on falling edge of SCK; enters high-Z when CS high or HOLD low. |
| WP (Pin 3) | Write-Protect Pin | Hardware lock: low disables all writes (array and STATUS register); overrides WEL state for fail-safe configuration integrity. |
| VSS (Pin 4) | Ground | Reference return path for all digital and analog functions; must be low-impedance to minimize noise coupling during write cycles. |
| SI (Pin 5) | Serial Data Input | Latches instructions, addresses, and data on rising edge of SCK; accepts MSb-first 8-bit sequences per SPI protocol. |
| SCK (Pin 6) | Serial Clock Input | Synchronizes all data transfers; timing parameters (Tsu, THD, TLO, THI) defined per VCC voltage tier for robustness across supply conditions. |
| HOLD (Pin 7) | Hold Input | Pauses ongoing SPI transaction: asserts high-Z on SO/SI/SCK while preserving internal address pointer and command state for interrupt servicing. |
| VCC (Pin 8) | Supply Voltage | Power input: supports 2.5–5.5 V; internal regulation enables stable EEPROM operation across battery voltage fluctuations in automotive systems. |
Key Features
| Feature | Design Value |
|---|---|
| Page Write Mode | Up to 16 bytes written atomically within one physical page (00h–0Fh, 10h–1Fh, etc.), reducing firmware overhead vs. byte-by-byte writes. |
| Block Write Protection | Selectable via STATUS register (BP0/BP1): protects none, upper 1/4 (60h–7Fh), upper 1/2 (40h–7Fh), or entire array (00h–7Fh) - prevents accidental overwrites of critical calibration data. |
| Built-in Write Protection | Combines power-on reset of WEL latch, WREN/WRDI instruction control, and WP pin hardware lock - multi-layer defense against unintended writes during brown-out or reset. |
| HOLD Functionality | Enables host MCU to suspend SPI transfer mid-sequence (e.g., during CAN interrupt), then resume without retransmitting address/instruction - preserves deterministic latency. |
| High Reliability | 1M endurance cycles and >200-year data retention verified per AEC-Q100 stress testing; ESD rating >4 kV HBM ensures robustness in noisy vehicle environments. |
Applications
| Engine Control Unit (ECU) | Advanced Driver Assistance Systems (ADAS) |
|---|---|
|
Use Scenario: Storing adaptive fuel trim values, misfire counters, and diagnostic trouble codes (DTCs) that persist across ignition cycles. IC Role / Device Role / Timing Role: Nonvolatile configuration memory interfaced directly to the ECU's SPI master; accessed during startup and runtime logging. Use Value: Automotive-grade temperature range and 1M endurance ensure reliable operation over 15+ year vehicle lifetimes despite thermal cycling and vibration. |
Use Scenario: Retaining camera calibration offsets, radar beamforming coefficients, and sensor fusion parameters in lane departure warning modules. IC Role / Device Role / Timing Role: SPI-configurable parameter store synchronized with MCU boot sequence; accessed before real-time image processing begins. Use Value: Page write mode reduces write time by 8× vs. byte writes, minimizing latency during critical sensor recalibration events. |
| Infotainment Head Unit | Body Control Module (BCM) |
|
Use Scenario: Saving user preferences (volume, EQ settings, Bluetooth pairing keys) and firmware update status flags. IC Role / Device Role / Timing Role: Low-power SPI EEPROM sharing bus with display driver and audio codec; selected only during UI initialization or update. Use Value: Standby current ≤5 µA at 5.5 V extends battery backup runtime during vehicle sleep mode (CAN/LIN bus off). |
Use Scenario: Storing door lock programming states, window auto-up/down thresholds, and lighting dimming profiles. IC Role / Device Role / Timing Role: Configuration memory accessed by 8-bit MCU over SPI; write-protected via WP pin to prevent corruption during power transients. Use Value: Hardware WP pin + STATUS register BP bits provide dual-layer protection against erroneous writes during EMI-heavy body network activity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar SPI EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 25AA010A-I/P | Wider VCC range (1.8–5.5 V); Industrial temp (−40°C to +85°C); same pinout and instruction set. | Not qualified for automotive underhood use; suitable for cabin electronics or industrial controls where extended voltage headroom is needed. | Select 25AA010A-I/P only if operating below 2.5 V or outside automotive temperature requirements. |
| AT25010B-SSH-T | Same 1 Kbit SPI EEPROM; 2.5–5.5 V; −40°C to +85°C; supports SPI Mode 0,0 only; no HOLD pin. | Lacks HOLD functionality and automotive temperature rating; lower ESD rating (2 kV HBM); not AEC-Q100 qualified. | Choose AT25010B-SSH-T only for cost-sensitive non-automotive designs where HOLD is unused and ambient temperature stays ≤85°C. |
Compared with 25AA010A-I/P and AT25010B-SSH-T, the 25LC010A-E/P uniquely delivers automotive-grade reliability (E-temp), integrated HOLD for interrupt-safe operation, and hardware WP pin - making it the sole choice for safety-critical powertrain and ADAS subsystems requiring guaranteed data integrity.
Availability
25LC010A-E/P is available at Aetrix Electronics and suitable for engine control units, ADAS sensor modules, and automotive infotainment systems requiring stable component supply across long production lifecycles.
Supply support for 25LC010A-E/P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontroller, mixed-signal, analog, and Flash-IP solutions, headquartered in Chandler, Arizona, with global design and manufacturing operations.
The 25LC010A belongs to Microchip's serial EEPROM product line, engineered specifically for automotive and industrial applications demanding high reliability, extended temperature operation, and robust SPI interface compliance.
FAQ
What is the maximum clock frequency supported by the 25LC010A-E/P?
The 25LC010A-E/P supports up to 10 MHz clock frequency when VCC is 4.5 V to 5.5 V. At 2.5 V ≤ VCC < 4.5 V, the maximum clock frequency is 5 MHz. These limits are specified in Table 1-2 of the DS21832H datasheet and ensure reliable setup/hold timing across automotive voltage ranges. The 25LC010A-E/P must be operated within these AC characteristics to guarantee correct read/write behavior.
Does the 25LC010A-E/P support page write operations, and what is the page size?
Yes, the 25LC010A-E/P supports page write mode with a fixed page size of 16 bytes. This allows up to 16 consecutive bytes to be loaded into the page buffer and written in a single internal cycle (≤5 ms). Physical page boundaries align to addresses ending in 0h–Fh (e.g., 00h–0Fh, 10h–1Fh), and crossing a boundary wraps data to the start of the same page - a behavior explicitly documented in the DS21832H functional description.
How does the HOLD pin function in the 25LC010A-E/P, and what design benefit does it provide?
The HOLD pin on the 25LC010A-E/P suspends ongoing SPI communication while preserving the internal address pointer and command state. When pulled low (with SCK low), SI/SO/SCK enter high-impedance, allowing the host MCU to service higher-priority interrupts without losing transaction context. This eliminates the need to restart SPI sequences, reducing firmware complexity and ensuring deterministic timing - especially valuable in real-time automotive systems using the 25LC010A-E/P.
What write protection mechanisms are implemented in the 25LC010A-E/P?
The 25LC010A-E/P implements three layered write protections: (1) hardware WP pin (Pin 3) that disables all writes when low; (2) volatile Write Enable Latch (WEL) set/reset via WREN/WRDI instructions; and (3) nonvolatile Block Protection bits (BP0/BP1) in the STATUS register controlling 0%, 25%, 50%, or 100% array lock. These are detailed in Tables 2-3 and 2-4 of DS21832H and collectively prevent accidental or malicious corruption of stored calibration data.
Is the 25LC010A-E/P qualified for automotive applications, and what temperature range does it support?
Yes, the 25LC010A-E/P carries the "E" suffix denoting Automotive qualification, with full operation guaranteed from −40°C to +125°C. This rating is validated per AEC-Q100 stress test requirements and confirmed in the Device Selection Table (page 1) and Electrical Characteristics (Table 1-1) of DS21832H. Its Pb-free, RoHS-compliant 8-lead PDIP package further supports automotive manufacturing standards.
25LC010A-E/P Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 1Kbit
- Memory Organization:
- 128 x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 10 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 8-PDIP
25LC010A-E/P FAQ
1.How can I place an order for 25LC010A-E/P through Aetrix?
Please submit a Request for Quotation (RFQ) for 25LC010A-E/P on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 25LC010A-E/P reliable?
The price and inventory of 25LC010A-E/P are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 25LC010A-E/P is usually 5 days.
3.What payment methods are accepted for 25LC010A-E/P?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 25LC010A-E/P transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 25LC010A-E/P?
25LC010A-E/P orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 25LC010A-E/P order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 25LC010A-E/P?
For technical support, including 25LC010A-E/P datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 25LC010A-E/P requirements.
6.How does Aetrix verify that 25LC010A-E/P is sourced from the original manufacturer or authorized distributors?
All 25LC010A-E/P products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 25LC010A-E/P meets industry standards.
7.What is the process for return or replacement of 25LC010A-E/P?
All 25LC010A-E/P units undergo pre-shipment inspection (PSI). If there is an issue with 25LC010A-E/P, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 25LC010A-E/P part is unused and in its original packaging.
Return procedure for 25LC010A-E/P:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
25LC010A-E/P Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

