Microchip Technology 25LC010A-I/SN
- Part No.:
- 25LC010A-I/SN
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
25LC010A-I/SN.pdf
- Description:
- IC EEPROM 1KBIT SPI 10MHZ 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:569
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
25LC010A-I/SN from Microchip Technology Inc. is a 1 Kbit (128 × 8) SPI Serial EEPROM with 16-byte page write capability, 10 MHz max clock frequency, and industrial temperature range (–40°C to +85°C). It features hardware write protection (WP pin), HOLD functionality for interrupt-safe pausing, and block-level write protection (none/¼/½/all array). Used in microcontroller-based systems for storing calibration data, configuration settings, or firmware parameters.
For engineers reviewing the 25LC010A-I/SN datasheet, 25LC010A-I/SN pinout, 25LC010A-I/SN application, or 25LC010A-I/SN equivalent, key selection criteria include VCC range (2.5–5.5V), SO/SI/SCK/CS/HOLD/WP/VSS/VCC 8-pin interface, 5 µA standby current, 5 ms max write cycle time, and 1M endurance cycles - critical for low-power embedded storage and field-updatable devices.
Technical Context
The 25LC010A-I/SN implements a standard SPI Mode 0,0 or Mode 1,1 interface with separate SI (data in) and SO (data out) lines, requiring CS assertion and SCK synchronization. Its internal architecture includes an 8-bit instruction register, page latches, and high-voltage generation circuitry for EEPROM programming.
Write operations require explicit WREN instruction followed by CS high-to-low transition to initiate self-timed internal write cycle (TWC ≤ 5 ms); status polling via RDSR (WIP bit) is supported. Block protection is controlled nonvolatively via BP0/BP1 bits in STATUS register, enabling selective 0%, 25%, 50%, or 100% array write-lock.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 1 Kbit (128 × 8 bits) - fits small configuration tables, device IDs, or sensor offsets without over-provisioning. |
| Interface | SPI-compatible serial bus (Mode 0,0 / Mode 1,1) - interoperable with PIC®, ARM Cortex-M, and most MCU SPI peripherals. |
| Max Clock Frequency | 10 MHz at VCC ≥ 4.5V - enables fast read/write bursts in time-critical boot or logging sequences. |
| Write Cycle Time | ≤ 5 ms per byte or page - deterministic timing allows precise host-side delay budgeting without polling overhead. |
| Endurance | 1,000,000 erase/write cycles - supports daily firmware updates or parameter logging for >27 years at 100 cycles/day. |
| Data Retention | > 200 years at 25°C - ensures long-term reliability for medical, industrial, or infrastructure equipment with infrequent access. |
| Supply Voltage | 2.5V to 5.5V - compatible with 3.3V logic systems and legacy 5V designs without level-shifting. |
Pinout & Package
25LC010A-I/SN is packaged in 8-lead SOIC (SN), with body dimensions 3.9 mm × 4.9 mm × 1.75 mm and standard JEDEC MS-012AC footprint. Pin 1 marked by laser dot or bevelled edge.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select Input | Active-low enable: drives device into active mode; rising edge after WRITE sequence triggers internal write cycle. |
| SO | Serial Data Output | Tri-state open-drain output: shares SPI bus with other slaves; high-impedance when CS high or HOLD low. |
| WP | Write-Protect Pin | Hardware lock: low = all writes (array & STATUS) disabled regardless of WEL state; overrides software protection. |
| VSS | Ground | Reference return path for all I/O and core logic; must be low-impedance to minimize noise during write operations. |
| SI | Serial Data Input | CMOS input latched on SCK rising edge: receives instructions (READ/WRITE/WREN/RDSR), addresses, and data bytes. |
| SCK | Serial Clock Input | Synchronization signal: defines timing for SI sampling and SO update; supports variable frequency up to 10 MHz. |
| HOLD | Hold Input | Interrupt-safe pause: low while SCK is low suspends ongoing SPI transfer; resumes from same bit position on next SCK edge. |
| VCC | Supply Voltage | Power rail: supplies core EEPROM, logic, and HV generator; bypass capacitor (0.1 µF) required near pin for stable write operation. |
Key Features
| Feature | Design Value |
|---|---|
| Page Write Mode (16 bytes) | Reduces write latency vs. byte-by-byte: 16x faster bulk updates for configuration blocks or calibration matrices. |
| Block Write Protection | Configurable via STATUS register (BP0/BP1): prevents accidental overwrite of critical sectors (e.g., bootloader config) while allowing user data updates. |
| Power-on Write Disable | WEL reset at power-up ensures no spurious writes occur during brown-out or supply ramp - eliminates need for external POR circuitry. |
| HOLD Functionality | Enables host MCU to service higher-priority interrupts mid-transfer without losing SPI context or re-synchronizing - critical for real-time control loops. |
| ESD Protection | > 4 kV HBM - withstands handling and board-level ESD events common in manufacturing and field service environments. |
Applications
| Industrial Sensor Calibration | Medical Device Configuration |
|---|---|
Use Scenario: Storing factory-calibrated gain/offset coefficients for analog front-end sensors in programmable logic controllers. IC Role / Device Role / Timing Role: Nonvolatile configuration store accessed during system boot and runtime recalibration; SPI interface synchronized to MCU clock. Use Value: Enables field-replaceable sensor modules with unique calibration data preserved across power cycles and firmware updates. | Use Scenario: Holding patient-specific therapy parameters (e.g., infusion rate limits, alarm thresholds) in portable insulin pumps. IC Role / Device Role / Timing Role: Secure, low-power parameter storage with WP pin hardwired to prevent unintended modification during operation. Use Value: Meets IEC 62304 safety requirements for data integrity; 200-year retention ensures lifetime device reliability without battery-backed RAM. |
| Automotive Body Control Module | Consumer Appliance Settings |
Use Scenario: Saving user preferences (mirror position, seat memory) and fault logs in 12V automotive BCMs operating across –40°C to +85°C. IC Role / Device Role / Timing Role: Industrial-grade EEPROM interfacing with CAN-connected MCU via SPI; HOLD used during CAN interrupt servicing. Use Value: Qualified for automotive temp range (I grade), 1M endurance supports 10+ years of daily use, and 2.5V min VCC tolerates cold-crank voltage dips. | Use Scenario: Retaining cooking presets, child lock status, and energy usage counters in smart ovens and washing machines. IC Role / Device Role / Timing Role: Cost-optimized serial NV storage connected to 3.3V MCU; WP pin tied to system enable signal for write lockdown during standby. Use Value: Low 5 µA standby current extends battery life in wireless remote interfaces; RoHS-compliant SN package meets global environmental regulations. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 25AA010A-I/SN | Wider VCC range (1.8–5.5V); supports 1.8V logic systems; identical pinout and instruction set. | Preferred for battery-powered or mixed-voltage designs where 1.8V operation is required. | Select when system VCC may drop below 2.5V; otherwise 25LC010A-I/SN offers same functionality at lower cost. |
| AT25010B-SSHL-T | Same 1 Kbit size, SPI interface, and 8-SOIC package; 20 MHz max clock; 5 ms write time; 1M endurance. | Drop-in alternative with higher speed margin; requires verification of HOLD/WP pin behavior per Atmel/Microchip cross-reference. | Valid for new designs needing higher clock headroom; not recommended for legacy 25LC010A-I/SN drop-in replacement without layout review. |
Compared with 25AA010A-I/SN and AT25010B-SSHL-T, the 25LC010A-I/SN provides optimal balance of industrial temperature rating, proven reliability in Microchip's ecosystem, and cost efficiency for 2.5–5.5V systems - making it the preferred choice for established designs and volume production.
Availability
25LC010A-I/SN is available at Aetrix Electronics and suitable for industrial sensor calibration, medical device configuration, and automotive body control modules requiring stable component supply and long-term lifecycle support.
Supply support for 25LC010A-I/SN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog, FPGA, and memory solutions, headquartered in Chandler, Arizona, with global design and manufacturing operations.
The 25LC010A belongs to Microchip's 25XX010A family of SPI Serial EEPROMs, designed specifically for reliable, low-power nonvolatile storage in resource-constrained embedded systems across industrial, medical, and automotive markets.
FAQ
What is the maximum clock frequency supported by the 25LC010A-I/SN?
The 25LC010A-I/SN supports a maximum clock frequency of 10 MHz when VCC is 4.5V to 5.5V. At 2.5V ≤ VCC < 4.5V, the limit drops to 5 MHz, and at 1.8V ≤ VCC < 2.5V, it is 3 MHz. These graded limits ensure reliable timing margins across its specified voltage range. The 25LC010A-I/SN datasheet (DS21832H) confirms these values in Table 1-2, AC Characteristics.
Does the 25LC010A-I/SN support page write operations, and what is the page size?
Yes, the 25LC010A-I/SN supports page write mode with a fixed page size of 16 bytes. This allows up to 16 sequential bytes to be loaded into the page buffer before initiating the internal write cycle. Writing across a page boundary wraps data to the start of the same page - a behavior explicitly documented in DS21832H-page 6. The 25LC010A-I/SN's 128-byte array contains eight physical pages (00h–0Fh, 10h–1Fh, ..., 70h–7Fh).
How does the WP pin function on the 25LC010A-I/SN, and can it override software write protection?
The WP (Write-Protect) pin on the 25LC010A-I/SN is a hardware-level disable: when pulled low, it inhibits all write operations to both memory array and STATUS register, regardless of WEL or BP bit states. This hard lock cannot be overridden by software commands like WREN or WRSR. The 25LC010A-I/SN datasheet (DS21832H-page 13) confirms WP takes precedence per the Write-Protect Functionality Matrix in Table 2-4.
What is the endurance and data retention specification for the 25LC010A-I/SN?
The 25LC010A-I/SN guarantees 1,000,000 erase/write cycles and data retention exceeding 200 years at 25°C. These figures are measured and specified in DS21832H-page 4 (Table 1-3, item 21) and page 1 (Features section). Endurance is tested at 25°C and VCC = 5.5V; retention is extrapolated from accelerated testing per JEDEC standards.
Is the 25LC010A-I/SN RoHS compliant and Pb-free?
Yes, the 25LC010A-I/SN is Pb-free and RoHS compliant, as stated in the Features section of DS21832H-page 1. The "SN" suffix denotes the 8-lead SOIC package with matte tin (Sn) finish, conforming to JEDEC J-STD-609A Class 1 marking. Full compliance documentation is available in Microchip's packaging specification referenced in DS21832H-page 17.
25LC010A-I/SN Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 1Kbit
- Memory Organization:
- 128 x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 10 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
25LC010A-I/SN FAQ
1.How can I place an order for 25LC010A-I/SN through Aetrix?
Please submit a Request for Quotation (RFQ) for 25LC010A-I/SN on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 25LC010A-I/SN reliable?
The price and inventory of 25LC010A-I/SN are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 25LC010A-I/SN is usually 5 days.
3.What payment methods are accepted for 25LC010A-I/SN?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 25LC010A-I/SN transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 25LC010A-I/SN?
25LC010A-I/SN orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 25LC010A-I/SN order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 25LC010A-I/SN?
For technical support, including 25LC010A-I/SN datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 25LC010A-I/SN requirements.
6.How does Aetrix verify that 25LC010A-I/SN is sourced from the original manufacturer or authorized distributors?
All 25LC010A-I/SN products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 25LC010A-I/SN meets industry standards.
7.What is the process for return or replacement of 25LC010A-I/SN?
All 25LC010A-I/SN units undergo pre-shipment inspection (PSI). If there is an issue with 25LC010A-I/SN, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 25LC010A-I/SN part is unused and in its original packaging.
Return procedure for 25LC010A-I/SN:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
25LC010A-I/SN Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
