Microchip Technology 25LC020A-E/ST
- Part No.:
- 25LC020A-E/ST
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
25LC020A-E/ST.pdf
- Description:
- IC EEPROM 2KBIT SPI 10MHZ 8TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:2,222
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
25LC020A-E/ST from Microchip Technology Inc. is a 2 Kbit SPI Serial EEPROM with 256 × 8-bit organization, 16-byte page write capability, and automotive-grade temperature support (−40°C to +125°C). It operates from 2.5V to 5.5V, supports up to 10 MHz clock frequency, and features hardware write protection via WP pin and HOLD functionality for interrupt-safe serial communication - used in engine control units and automotive sensor calibration storage.
For engineers reviewing the 25LC020A-E/ST datasheet, 25LC020A-E/ST pinout, 25LC020A-E/ST application, or 25LC020A-E/ST equivalent, key selection criteria include VCC range compatibility (2.5–5.5V), automotive temperature rating (E grade), SOIC-8 package footprint, SPI timing compliance at 10 MHz, and nonvolatile block protection configuration (BP0/BP1 bits).
Technical Context
The 25LC020A-E/ST implements a standard SPI Mode 0,0 or Mode 1,1 interface with separate SI/SO lines and CS-controlled device selection. Its internal architecture includes an 8-bit instruction register, page latches, and high-voltage generation circuitry for EEPROM programming, enabling byte- and page-write operations with automatic address incrementing during sequential reads.
Write enable is controlled by a volatile WEL bit set via WREN instruction and reset on power-up, WRDI, WRSR, or successful WRITE. Block protection is managed through nonvolatile BP0/BP1 bits in the STATUS register, allowing selective write-protection of 0%, 25%, 50%, or 100% of the memory array - critical for firmware parameter safeguarding in safety-critical automotive systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 2 Kbit (256 × 8-bit) - fits calibration tables, VIN/EVIN data, and small firmware patches in space-constrained ECUs. |
| Interface | SPI-compatible serial bus (Mode 0,0 / Mode 1,1) - interoperable with PIC® and ARM Cortex-M microcontrollers without protocol translation. |
| Max Clock Frequency | 10 MHz at VCC ≥ 4.5V - enables fast parameter loading during vehicle startup or reprogramming cycles. |
| Write Cycle Time | ≤5 ms per byte or page - deterministic erase/write latency supports time-bound diagnostic logging. |
| Endurance & Retention | 1,000,000 erase/write cycles and >200 years data retention - meets ASIL-B functional safety requirements for long-life automotive deployment. |
| Temperature Range | −40°C to +125°C (Automotive E grade) - qualified for under-hood and transmission control module environments. |
| VCC Operating Range | 2.5V to 5.5V - compatible with 3.3V and 5V automotive power domains without level-shifting. |
Pinout & Package
25LC020A-E/ST is packaged in 8-lead SOIC (ST suffix), with 1.27 mm pitch, 5.0 mm × 4.0 mm body size, and Pb-free/RoHS-compliant finish. Pin 1 is marked by laser indentation per JEDEC MS-012.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS (Pin 1) | Chip Select Input | Active-low enable signal; must be low for all SPI transactions; rising edge initiates internal write cycle after valid command sequence. |
| SO (Pin 2) | Serial Data Output | Tri-state output delivering read data on falling SCK edge; high-impedance when CS = high or HOLD = low. |
| WP (Pin 3) | Write-Protect Pin | Hardware lock: low disables all writes to memory and STATUS register regardless of WEL state - critical for preventing corruption during voltage transients. |
| VSS (Pin 4) | Ground | Reference return path for all digital and internal HV programming circuits; must be low-impedance for reliable write margin. |
| SI (Pin 5) | Serial Data Input | Accepts instructions, addresses, and write data on rising SCK edge; sampled only when CS = low and HOLD = high. |
| SCK (Pin 6) | Serial Clock Input | Master-generated clock synchronizing all SPI transfers; rise/fall times ≤100 ns required for 10 MHz operation. |
| HOLD (Pin 7) | Hold Input | Pauses ongoing SPI transfer without resetting state; allows host MCU to service higher-priority interrupts while preserving transaction context. |
| VCC (Pin 8) | Supply Voltage | Primary power rail (2.5–5.5V); powers logic, HV generator, and I/O buffers; decoupling capacitor mandatory near pin. |
Key Features
| Feature | Design Value |
|---|---|
| Page Write Mode (16 bytes) | Reduces write overhead by 16× vs. byte writes - accelerates bulk parameter updates like adaptive learning maps in real-time engine tuning. |
| Block Write Protection (BP0/BP1) | Configurable nonvolatile lock of upper 25%/50% or full array - prevents accidental overwrite of factory-calibrated trim values during field service. |
| Power-On Write Disable | WEL latch resets at power-up, requiring explicit WREN before any write - eliminates spurious writes during brown-out or cold-start conditions. |
| HOLD Functionality | Enables deterministic pause/resume of multi-byte SPI transfers - essential for deterministic interrupt response in AUTOSAR OS-based ECUs. |
| ESD Robustness | ≥4 kV HBM - withstands handling and assembly stresses in automotive manufacturing environments without additional protection circuitry. |
Applications
| Engine Control Unit (ECU) | Advanced Driver Assistance Systems (ADAS) |
|---|---|
Use Scenario: Storing adaptive fuel trim coefficients and misfire history across ignition cycles. IC Role / Device Role / Timing Role: Nonvolatile parameter storage with deterministic 5 ms write latency and automotive-grade reliability. Use Value: Enables closed-loop engine optimization without external backup power or complex wear-leveling firmware. |
Use Scenario: Retaining camera calibration offsets and radar sensor alignment data after vehicle shutdown. IC Role / Device Role / Timing Role: SPI-accessible EEPROM interfacing directly with ADAS SoC's SPI master port. Use Value: Eliminates need for battery-backed SRAM; maintains calibration integrity over 15+ year vehicle lifetime. |
| Transmission Control Module (TCM) | Body Control Module (BCM) |
Use Scenario: Logging gear shift adaptation profiles and clutch wear metrics for predictive maintenance. IC Role / Device Role / Timing Role: High-endurance (1M cycles) memory supporting frequent runtime updates in harsh thermal environments. Use Value: Supports ASIL-B compliant diagnostics without compromising update frequency or data fidelity. |
Use Scenario: Storing user-configurable lighting sequences, window auto-up/down positions, and door lock preferences. IC Role / Device Role / Timing Role: Low-power (5 µA standby) serial EEPROM accessed via BCM's SPI peripheral during sleep mode wake events. Use Value: Enables personalized settings persistence with minimal quiescent current impact on 12V battery drain. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar SPI EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 25AA020A-I/ST | Wider VCC range (1.8–5.5V); Industrial temp only (−40°C to +85°C); identical pinout and instruction set. | Not qualified for under-hood automotive use; suitable for cabin electronics or industrial control panels. | Select only if 1.8V operation or extended low-VCC margin is required and automotive temperature rating is unnecessary. |
| AT25020B-SSHL-T | Same 2 Kbit SPI EEPROM; 2.5–5.5V; −40°C to +85°C; different STATUS register layout and no HOLD pin. | Lacks HOLD functionality and automotive temperature grade; requires software polling instead of hardware pause. | Choose only for cost-sensitive non-automotive designs where HOLD is unused and temperature range is sufficient. |
Compared with 25LC020A-E/ST, the 25AA020A-I/ST offers broader voltage flexibility but lacks automotive qualification, while the AT25020B-SSHL-T omits HOLD and BP granularity - making 25LC020A-E/ST the sole option meeting full ASIL-B EEPROM requirements with hardware-assisted reliability features.
Availability
25LC020A-E/ST is available at Aetrix Electronics and suitable for engine control units, ADAS sensor modules, and transmission control systems requiring stable component supply across extended automotive product lifecycles.
Supply support for 25LC020A-E/ST includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontroller, analog, and memory solutions, headquartered in Chandler, Arizona, with global design and manufacturing operations.
The 25LC020A belongs to Microchip's serial EEPROM product line, engineered specifically for automotive and industrial applications demanding high reliability, extended temperature operation, and robust SPI interface compliance.
FAQ
What is the maximum clock frequency supported by the 25LC020A-E/ST?
The 25LC020A-E/ST supports up to 10 MHz clock frequency when VCC is 4.5V to 5.5V. At 2.5V ≤ VCC < 4.5V, the maximum clock frequency is 5 MHz. These limits are defined in Table 1-2 of the DS21833G datasheet and ensure reliable setup/hold timing margins across the full automotive temperature range.
Does the 25LC020A-E/ST require external pull-up resistors on its SPI lines?
The 25LC020A-E/ST does not require external pull-ups on SI, SO, or SCK - these pins are driven actively by the host and device. However, CS and WP should be pulled high via 10 kΩ resistors to VCC in most automotive designs to ensure defined logic states during power-up and noise immunity, as recommended in Microchip Application Note AN1179.
How does the HOLD function operate during an active SPI transaction in the 25LC020A-E/ST?
In the 25LC020A-E/ST, pulling HOLD low while SCK is low pauses the SPI transaction without resetting internal state. SI, SCK, and SO enter high-impedance, and input transitions are ignored except for CS. Resuming requires bringing HOLD high while SCK remains low - then communication continues from the exact bit position where it was paused, preserving full transaction integrity.
What memory protection mechanisms are implemented in the 25LC020A-E/ST?
The 25LC020A-E/ST implements three layered protections: (1) hardware WP pin disabling all writes when low; (2) volatile WEL bit requiring WREN instruction before writes; and (3) nonvolatile BP0/BP1 bits enabling configurable write-protection of 0%, 25%, 50%, or 100% of the 256-byte array - all verified in DS21833G Sections 2.4–2.6.
Is the 25LC020A-E/ST pin-compatible with the 25AA020A-I/ST?
Yes, the 25LC020A-E/ST and 25AA020A-I/ST share identical 8-lead SOIC (ST) package pinout, instruction set, and SPI timing behavior. The only differences are VCC range (2.5–5.5V vs. 1.8–5.5V) and temperature grade (E vs. I), making them drop-in replacements in hardware layout - though firmware must validate voltage and thermal operating boundaries.
25LC020A-E/ST Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 2Kbit
- Memory Organization:
- 256 x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 10 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
25LC020A-E/ST FAQ
1.How can I place an order for 25LC020A-E/ST through Aetrix?
Please submit a Request for Quotation (RFQ) for 25LC020A-E/ST on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 25LC020A-E/ST reliable?
The price and inventory of 25LC020A-E/ST are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 25LC020A-E/ST is usually 5 days.
3.What payment methods are accepted for 25LC020A-E/ST?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 25LC020A-E/ST transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 25LC020A-E/ST?
25LC020A-E/ST orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 25LC020A-E/ST order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 25LC020A-E/ST?
For technical support, including 25LC020A-E/ST datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 25LC020A-E/ST requirements.
6.How does Aetrix verify that 25LC020A-E/ST is sourced from the original manufacturer or authorized distributors?
All 25LC020A-E/ST products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 25LC020A-E/ST meets industry standards.
7.What is the process for return or replacement of 25LC020A-E/ST?
All 25LC020A-E/ST units undergo pre-shipment inspection (PSI). If there is an issue with 25LC020A-E/ST, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 25LC020A-E/ST part is unused and in its original packaging.
Return procedure for 25LC020A-E/ST:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
25LC020A-E/ST Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
