Microchip Technology 25LC020AT-E/SN
- Part No.:
- 25LC020AT-E/SN
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
25LC020AT-E/SN.pdf
- Description:
- IC EEPROM 2KBIT SPI 10MHZ 8SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
25LC020AT-E/SN from Microchip Technology Inc. is a 2 Kbit (256 × 8) SPI Serial EEPROM with 16-byte page write capability, 10 MHz max clock frequency at 4.5–5.5 V, and industrial/automotive temperature support (−40°C to +125°C). It features hardware write protection (WP pin), HOLD functionality for interrupt-safe pausing, and block protection covering none/¼/½/all memory array - used in embedded system configuration storage, sensor calibration data retention, and firmware parameter backup.
For engineers reviewing the 25LC020AT-E/SN datasheet, 25LC020AT-E/SN pinout, 25LC020AT-E/SN application, or 25LC020AT-E/SN equivalent, key selection criteria include VCC range (2.5–5.5 V), automotive-grade reliability (1M endurance, >200-year data retention), SPI Mode 0/1 compatibility, and SOIC-8 (SN) package footprint with verified pin mapping.
Technical Context
The 25LC020AT-E/SN implements a standard SPI interface with separate SI (data in), SO (data out), SCK (clock), CS (chip select), WP (write-protect), and HOLD (pause) signals. It operates in SPI Modes 0,0 and 1,1 per Figure 1-2 and Figure 1-3, supporting MSb-first serial transfer and automatic address increment during sequential reads.
Internally, it uses an 8-bit instruction register, nonvolatile STATUS register (WIP/WEL/BP0/BP1 bits), and page latches enabling up to 16-byte writes within fixed 16-byte physical pages. Write cycles are self-timed (≤5 ms), and the device enters high-impedance SO state when deselected or held.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 2 Kbit (256 × 8) - fits small configuration tables, device IDs, or calibration coefficients in space-constrained designs. |
| Interface | SPI-compatible serial bus - requires only 4 signal lines (CS, SCK, SI, SO) plus optional WP/HOLD, minimizing MCU GPIO usage. |
| Max Clock Frequency | 10 MHz at VCC ≥ 4.5 V - enables fast read/write bursts without requiring high-speed MCU peripherals. |
| Write Cycle Time | ≤5 ms per byte or page - deterministic timing allows precise software polling via WIP bit; no external wait-state logic needed. |
| Endurance & Retention | 1,000,000 erase/write cycles; >200 years data retention - qualified for automotive and industrial field-deployed systems. |
| VCC Range | 2.5 V to 5.5 V - interoperable with 3.3 V and 5 V logic domains; supports brown-out tolerant operation down to 2.5 V. |
| Temperature Range | −40°C to +125°C (Automotive E grade) - validated for under-hood, powertrain, and motor control environments. |
Pinout & Package
25LC020AT-E/SN is packaged in 8-lead SOIC (SN), with 1.27 mm pitch, 5.0 mm × 4.0 mm body, and Pb-free/RoHS-compliant finish. Pin 1 marked by laser dot or notch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (CS) | Chip Select Input | Active-low enable: drives device into active mode; rising edge initiates internal write cycle after valid command sequence. |
| 2 (SO) | Serial Data Output | Tri-state open-drain output: delivers read data on falling SCK edge; high-impedance when CS high or HOLD low. |
| 3 (WP) | Write-Protect Input | Hardware lock: low disables all writes to memory and STATUS register, overriding WEL state per Table 2-4. |
| 4 (VSS) | Ground Reference | Primary return path for all I/O and core logic; must be low-impedance connection to avoid noise-induced corruption. |
| 5 (SI) | Serial Data Input | CMOS input: latches instruction/address/data on rising SCK edge; accepts 0.2×VCC–0.3 V to 0.7×VCC logic thresholds. |
| 6 (SCK) | Serial Clock Input | Synchronous timing reference: defines data sampling (SI) and output update (SO) edges; max 10 MHz at VCC ≥ 4.5 V. |
| 7 (HOLD) | Hold Input | Pause control: low suspends ongoing SPI transaction (ignores SI/SCK) while preserving internal state; resumes on rising edge while SCK low. |
| 8 (VCC) | Supply Voltage | Core power rail: powers EEPROM array, logic, and HV generator; bypass capacitor (0.1 µF) required near pin for stable write operations. |
Key Features
| Feature | Design Value |
|---|---|
| Page Write (16 bytes) | Reduces write overhead by 16× vs. byte-write: one CS assertion covers full page, minimizing SPI transaction count and host CPU load. |
| Block Write Protection | BP0/BP1 bits in STATUS register allow selective locking of upper ¼, ½, or entire 256-byte array - prevents accidental firmware or calibration overwrite. |
| HOLD Functionality | Enables MCU to service higher-priority interrupts mid-transaction without losing context or re-synchronizing SPI framing. |
| Power-On Write Disable | Write enable latch resets at power-up, preventing spurious writes during supply ramp; explicit WREN required before any programming. |
| ESD Robustness | ≥4 kV HBM rating on all pins - eliminates need for external TVS diodes in typical industrial PCB layouts. |
Applications
| Industrial PLC Configuration Storage | Automotive Sensor Calibration |
|---|---|
Use Scenario: Storing I/O mapping, scaling factors, and alarm thresholds in programmable logic controllers subject to frequent power cycling. IC Role / Device Role / Timing Role: Nonvolatile configuration register accessed via SPI during boot or runtime reconfiguration; retains values across 10+ year deployments. Use Value: Eliminates battery-backed SRAM; leverages 1M endurance and >200-year retention to guarantee parameter integrity without maintenance. | Use Scenario: Recording factory-trimmed offset/gain values for pressure, temperature, and position sensors in engine control units. IC Role / Device Role / Timing Role: Calibration data vault written once during end-of-line test; read-only during vehicle operation; protected by WP pin and BP bits. Use Value: Ensures sensor accuracy over full automotive lifetime (−40°C to +125°C), with hardware write lock preventing field corruption. |
| Medical Device Parameter Backup | Smart Energy Meter Firmware Settings |
Use Scenario: Saving user-adjustable therapy parameters (e.g., infusion rate, alarm limits) in portable infusion pumps with infrequent updates. IC Role / Device Role / Timing Role: Low-power SPI EEPROM interfaced to ARM Cortex-M0+ MCU; accessed only during setup or error recovery. Use Value: 5 µA standby current extends battery life; 2.5 V min VCC ensures operation during brown-out conditions. | Use Scenario: Storing tariff schedules, communication keys, and metering constants in ANSI C12.19-compliant smart meters deployed in harsh outdoor environments. IC Role / Device Role / Timing Role: Secure settings repository with WP pin tied to microcontroller GPIO for dynamic lock/unlock; accessed via isolated SPI bus. Use Value: Automotive-grade temperature rating and 4 kV ESD withstand ensure reliability in utility-grade enclosures with high EMI exposure. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 25AA020AT-I/SN | VCC range 1.8–5.5 V; Industrial temp only (−40°C to +85°C); same pinout and instruction set. | Lacks automotive qualification; unsuitable for under-hood or powertrain use cases requiring 125°C operation. | Select when cost-sensitive industrial designs operate below 85°C and require wider voltage flexibility (e.g., 1.8 V MCUs). |
| AT25020B-MAHL-T | Same 2 Kbit size, SPI interface, and SOIC-8 package; AEC-Q100 Grade 2 (−40°C to +105°C); 20 MHz max clock. | Higher speed but narrower temp range than 25LC020AT-E/SN; different STATUS register layout and write-protection scheme. | Choose when 105°C suffices and faster clocking improves throughput; verify BP bit mapping and WRSR behavior before migration. |
Compared with 25AA020AT-I/SN, the 25LC020AT-E/SN adds automotive temperature support and tighter VCC min (2.5 V), while AT25020B-MAHL-T offers higher speed but lacks full 125°C qualification - making 25LC020AT-E/SN the only option meeting AEC-Q100 Grade 0 requirements among these three.
Availability
25LC020AT-E/SN is available at Aetrix Electronics and suitable for industrial PLCs, automotive ECUs, medical infusion devices, and smart energy meters requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for 25LC020AT-E/SN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog, FPGA, and memory solutions, headquartered in Chandler, Arizona, with global design and manufacturing operations.
The 25LC020A family is designed for reliable, low-power nonvolatile data storage in resource-constrained embedded systems - emphasizing SPI simplicity, automotive-grade robustness, and long-term data integrity.
FAQ
What is the maximum clock frequency supported by the 25LC020AT-E/SN, and how does it vary with supply voltage?
The 25LC020AT-E/SN supports up to 10 MHz at VCC = 4.5–5.5 V, 5 MHz at VCC = 2.5–4.5 V, and is not rated below 2.5 V. These limits are defined in Table 1-2 AC Characteristics and ensure reliable setup/hold timing across the automotive temperature range. The 25LC020AT-E/SN must not be operated above 10 MHz even at 5.5 V unless validated per application-specific characterization.
How does the HOLD pin function during an active SPI transaction in the 25LC020AT-E/SN?
When the HOLD pin is pulled low during an active SPI transaction (with CS low and SCK stable low), the 25LC020AT-E/SN immediately tri-states SO and ignores further SI/SCK transitions while preserving internal state. Communication resumes on the next rising edge of HOLD, provided SCK remains low - enabling the host MCU to service interrupts without reinitializing the SPI frame. This behavior is confirmed in Section 2.8 and Figure 1-1.
Can the 25LC020AT-E/SN perform page writes across 16-byte boundaries, and what happens if attempted?
No - page writes in the 25LC020AT-E/SN are strictly confined to 16-byte physical pages (addresses 00h–0Fh, 10h–1Fh, etc.). If a page write command crosses a boundary (e.g., writing 16 bytes starting at address 0Fh), data wraps to the start of the same page (00h), overwriting prior contents. This wrap behavior is explicitly documented in Section 2.3 and Note on DS21833G-page 6.
What write protection mechanisms are implemented in the 25LC020AT-E/SN, and how do they interact?
The 25LC020AT-E/SN implements three layered protections: (1) WP pin (hardware lock), (2) WEL bit (software-gated write enable), and (3) BP0/BP1 bits (nonvolatile block lock). Per Table 2-4, WP low overrides WEL and blocks all writes regardless of STATUS register state. WEL must be set via WREN before any write, and BP bits define protected address ranges - all verified in Sections 2.4–2.6 and DS21833G-page 10–11.
Is the 25LC020AT-E/SN pin-compatible with other members of the 25XX020A family, such as the 25AA020A?
Yes - the 25LC020AT-E/SN shares identical pinout, package dimensions, and SPI protocol with all 25XX020A variants (including 25AA020A, 25LC020A) in SOIC-8 (SN) packaging, as confirmed in the Device Selection Table and Pin Function Table (DS21833G-page 1–2, 13). Functional differences (VCC range, temp grade) do not affect physical or electrical pin compatibility.
25LC020AT-E/SN Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 2Kbit
- Memory Organization:
- 256 x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 10 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
25LC020AT-E/SN FAQ
1.How can I place an order for 25LC020AT-E/SN through Aetrix?
Please submit a Request for Quotation (RFQ) for 25LC020AT-E/SN on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 25LC020AT-E/SN reliable?
The price and inventory of 25LC020AT-E/SN are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 25LC020AT-E/SN is usually 5 days.
3.What payment methods are accepted for 25LC020AT-E/SN?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 25LC020AT-E/SN transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 25LC020AT-E/SN?
25LC020AT-E/SN orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 25LC020AT-E/SN order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 25LC020AT-E/SN?
For technical support, including 25LC020AT-E/SN datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 25LC020AT-E/SN requirements.
6.How does Aetrix verify that 25LC020AT-E/SN is sourced from the original manufacturer or authorized distributors?
All 25LC020AT-E/SN products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 25LC020AT-E/SN meets industry standards.
7.What is the process for return or replacement of 25LC020AT-E/SN?
All 25LC020AT-E/SN units undergo pre-shipment inspection (PSI). If there is an issue with 25LC020AT-E/SN, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 25LC020AT-E/SN part is unused and in its original packaging.
Return procedure for 25LC020AT-E/SN:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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