Microchip Technology 25LC040AT-E/MC
- Part No.:
- 25LC040AT-E/MC
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-VFDFN Exposed Pad
- Datasheet:
-
25LC040AT-E/MC.pdf
- Description:
- IC EEPROM 4KBIT SPI 10MHZ 8DFN
- Quantity:
- Payment:

- Shipping:

Inventory:3,290
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
25LC040AT-E/MC from Microchip Technology Inc. is a 4 Kbit SPI Serial EEPROM with 512 × 8-bit organization, 16-byte page write capability, and industrial-temperature operation (–40°C to +85°C). It supports up to 10 MHz clock frequency at 4.5–5.5 V, features hardware write protection via WP pin, and delivers 1 million erase/write cycles with >200-year data retention. It is used in microcontroller-based systems for storing calibration data, configuration settings, and firmware parameters.
For engineers reviewing the 25LC040AT-E/MC datasheet, 25LC040AT-E/MC pinout, 25LC040AT-E/MC application, or 25LC040AT-E/MC equivalent, key selection criteria include SPI interface compatibility, 2.5–5.5 V supply range, HOLD functionality for interrupt-safe bus sharing, block-level write protection (BP0/BP1), and DFN-8 (2×3 mm) package suitability for space-constrained PCB layouts.
Technical Context
The 25LC040AT-E/MC implements a standard SPI Mode 0,0 or Mode 1,1 interface with separate SI (data in) and SO (data out) lines, controlled by CS, SCK, and optional HOLD. Its internal architecture includes a 512-byte EEPROM array, page latches, status register (WIP/WEL/BP0/BP1), and high-voltage generator for write/erase operations.
Write operations require explicit WREN instruction followed by CS high to latch enable state; writes are self-timed (≤5 ms), and page boundaries (16-byte aligned) must be respected to avoid wraparound. The HOLD pin suspends ongoing serial transfers without resetting sequence state, enabling host CPU to service higher-priority interrupts while preserving transaction context.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 4 Kbit (512 × 8-bit), sufficient for small configuration tables or device ID storage in resource-limited embedded systems |
| Interface | SPI-compatible serial bus (Mode 0,0 / Mode 1,1), requiring only CS, SCK, SI, SO, WP, HOLD, VCC, VSS - no parallel bus overhead |
| Max Clock Frequency | 10 MHz at VCC ≥ 4.5 V, enabling fast read/write bursts in high-throughput MCU applications |
| Write Cycle Time | ≤5 ms per byte or page, deterministic timing simplifies firmware polling or timeout handling |
| Endurance & Retention | 1,000,000 erase/write cycles and >200 years data retention at 25°C, validated for long-life industrial deployments |
| Supply Voltage Range | 2.5 V to 5.5 V, compatible with both 3.3 V and 5 V logic domains without level-shifting |
| Operating Temperature | –40°C to +85°C (Industrial grade), qualified for use in automotive body control modules and industrial PLCs |
Pinout & Package
25LC040AT-E/MC is housed in an 8-lead 2×3 mm DFN (Dual Flat No-lead) package with exposed pad, optimized for thermal performance and board space efficiency in compact designs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (CS) | Chip Select Input | Active-low enable signal; drives device into active mode and initiates command decoding on falling edge |
| 2 (SO) | Serial Data Output | Tri-state output delivering read data MSB-first on SCK falling edge; high-impedance when CS high or HOLD low |
| 3 (WP) | Write-Protect Pin | Hardware lock: low disables all writes to memory and STATUS register regardless of WEL state |
| 4 (VSS) | Ground | Reference return path for all digital and internal analog circuitry; connected to exposed pad for thermal conduction |
| 5 (SI) | Serial Data Input | Accepts instructions, addresses, and write data MSB-first on SCK rising edge |
| 6 (SCK) | Serial Clock Input | Master-generated clock synchronizing all serial transfers; defines timing for SI sampling and SO updates |
| 7 (HOLD) | Hold Input | Pauses ongoing SPI transfer when pulled low during active CS; preserves internal address pointer and command state |
| 8 (VCC) | Supply Voltage | Primary power rail (2.5–5.5 V); powers internal logic, HV generator, and I/O buffers |
Key Features
| Feature | Design Value |
|---|---|
| Page Write Mode | Up to 16 bytes written per command, reducing SPI transaction count and improving firmware efficiency over byte-by-byte writes |
| Block Write Protection | Configurable via STATUS register (BP0/BP1) to protect none, upper 1/4, upper 1/2, or entire 512-byte array against accidental overwrite |
| Power-On Write Protection | Write enable latch resets at power-up, preventing spurious writes during supply ramp-up or brownout conditions |
| HOLD Functionality | Enables non-disruptive suspension of SPI communication, allowing host MCU to handle time-critical interrupts without reinitializing the transfer |
| Low Standby Current | 1 µA at 2.5 V and +85°C, minimizing quiescent power draw in battery-backed or energy-sensitive applications |
Applications
| Smart Sensor Calibration Storage | Industrial PLC Configuration Memory |
|---|---|
Use Scenario: Storing factory-calibrated sensor offset/gain coefficients and temperature compensation tables in MEMS pressure or temperature sensors. IC Role / Device Role / Timing Role: Nonvolatile configuration store accessed during sensor power-up or recalibration routines via SPI from host MCU. Use Value: Enables field-replaceable sensor modules with persistent calibration data across power cycles and firmware updates. | Use Scenario: Retaining user-defined I/O mapping, alarm thresholds, and scheduling parameters in modular programmable logic controllers. IC Role / Device Role / Timing Role: Dedicated parameter EEPROM interfaced to PLC's main controller over shared SPI bus with HOLD support for real-time task preemption. Use Value: Ensures deterministic configuration persistence without volatile RAM backup, supporting unattended operation for >200 years. |
| Automotive Body Control Module | Medical Device Usage Log |
Use Scenario: Recording seat position memory, mirror presets, and lighting profiles in automotive door modules operating across –40°C to +85°C. IC Role / Device Role / Timing Role: Industrial-grade SPI EEPROM providing robust, low-power storage for user preferences with hardware WP pin tied to system security state. Use Value: Meets AEC-Q100 stress requirements indirectly via industrial temp grade and 1M-cycle endurance, reducing qualification effort. | Use Scenario: Logging sterilization cycles, usage hours, and error events in portable diagnostic equipment requiring FDA-compliant traceability. IC Role / Device Role / Timing Role: Tamper-resistant event logger with BP1/BP0 bits set to lock critical log segments after write, enforced by WP pin during normal operation. Use Value: Provides auditable, nonvolatile history with hardware+software write protection layers meeting IEC 62304 data integrity requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 25AA040AT-I/MC | Wider VCC range (1.8–5.5 V); same pinout, timing, and capacity; rated for Industrial temp only (–40°C to +85°C) | Supports 1.8 V logic systems (e.g., ultra-low-power MCUs); not qualified for automotive E-temp applications | Select when interfacing with 1.8 V or mixed-voltage SPI buses where 25LC040AT-E/MC's 2.5 V minimum is incompatible |
| AT25040B-MAHL-T | Same 4 Kbit SPI EEPROM, 8-lead SOIC package; 2.5–5.5 V, 10 MHz max, but uses different STATUS register bit layout and lacks HOLD pin | No HOLD functionality limits interrupt-safe operation; SOIC footprint requires larger PCB area than DFN-8 | Choose when board space allows SOIC and HOLD is unnecessary; verify STATUS register compatibility before firmware porting |
Compared with 25LC040AT-E/MC, the 25AA040AT-I/MC extends voltage flexibility downward to 1.8 V but sacrifices automotive qualification, while AT25040B-MAHL-T trades HOLD support and compact DFN packaging for broader distributor availability in legacy SOIC form.
Availability
25LC040AT-E/MC is available at Aetrix Electronics and suitable for industrial automation, automotive body electronics, and medical diagnostics requiring stable component supply, long-term data retention, and compact 2×3 mm DFN packaging.
Supply support for 25LC040AT-E/MC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog devices, and memory solutions, headquartered in Chandler, Arizona, with global design and manufacturing operations.
The 25LC040A family was designed for reliable, low-power nonvolatile storage in cost-sensitive embedded systems requiring SPI interface simplicity, hardware write protection, and extended endurance - targeting industrial control, automotive subsystems, and consumer electronics.
FAQ
What is the maximum clock frequency supported by the 25LC040AT-E/MC?
The 25LC040AT-E/MC supports a maximum clock frequency of 10 MHz when VCC is between 4.5 V and 5.5 V. At lower supply voltages (2.5–4.5 V), the maximum clock rate reduces to 5 MHz. These values are specified in Table 1-2 of the DS21827H datasheet and reflect guaranteed AC timing performance across the full industrial temperature range.
Does the 25LC040AT-E/MC have a HOLD pin, and how is it used?
Yes, the 25LC040AT-E/MC includes a dedicated HOLD pin (Pin 7). When pulled low while CS is active and SCK is low, it pauses ongoing SPI communication without resetting the internal address pointer or command state. This allows the host MCU to service higher-priority interrupts and resume the exact same transfer upon releasing HOLD - a critical feature for real-time embedded systems using the 25LC040AT-E/MC.
What package type is used for the 25LC040AT-E/MC?
The 25LC040AT-E/MC uses an 8-lead 2×3 mm DFN (Dual Flat No-lead) package with exposed thermal pad (package code MC). This compact, surface-mount package provides excellent thermal performance and board space efficiency, making it ideal for dense PCB layouts in industrial and automotive applications where the 25LC040AT-E/MC is deployed.
How many write/erase cycles does the 25LC040AT-E/MC guarantee?
The 25LC040AT-E/MC guarantees 1,000,000 erase/write cycles per memory location, as confirmed in Table 1-3 (Parameter 21) of the DS21827H datasheet. This endurance rating is specified at 25°C and VCC = 5.5 V, and supports long-term reliability in applications such as firmware parameter logging and calibration storage where the 25LC040AT-E/MC undergoes frequent updates.
Can the 25LC040AT-E/MC operate from a 3.3 V supply?
Yes, the 25LC040AT-E/MC operates reliably from a 3.3 V supply, as its specified VCC range is 2.5 V to 5.5 V. At 3.3 V, it supports up to 5 MHz SPI clock frequency (per Table 1-2, Param 1) and maintains full functionality including HOLD, WP, and STATUS register access. This makes the 25LC040AT-E/MC well-suited for modern 3.3 V microcontroller platforms.
25LC040AT-E/MC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-VFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 4Kbit
- Memory Organization:
- 512 x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 10 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-DFN (2x3)
25LC040AT-E/MC FAQ
1.How can I place an order for 25LC040AT-E/MC through Aetrix?
Please submit a Request for Quotation (RFQ) for 25LC040AT-E/MC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 25LC040AT-E/MC reliable?
The price and inventory of 25LC040AT-E/MC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 25LC040AT-E/MC is usually 5 days.
3.What payment methods are accepted for 25LC040AT-E/MC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 25LC040AT-E/MC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 25LC040AT-E/MC?
25LC040AT-E/MC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 25LC040AT-E/MC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 25LC040AT-E/MC?
For technical support, including 25LC040AT-E/MC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 25LC040AT-E/MC requirements.
6.How does Aetrix verify that 25LC040AT-E/MC is sourced from the original manufacturer or authorized distributors?
All 25LC040AT-E/MC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 25LC040AT-E/MC meets industry standards.
7.What is the process for return or replacement of 25LC040AT-E/MC?
All 25LC040AT-E/MC units undergo pre-shipment inspection (PSI). If there is an issue with 25LC040AT-E/MC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 25LC040AT-E/MC part is unused and in its original packaging.
Return procedure for 25LC040AT-E/MC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
25LC040AT-E/MC Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
