Microchip Technology 25LC080AT-E/ST
- Part No.:
- 25LC080AT-E/ST
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
25LC080AT-E/ST.pdf
- Description:
- IC EEPROM 8KBIT SPI 10MHZ 8TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:2,582
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Product details
Overview
25LC080AT-E/ST from Microchip Technology Inc. is an 8 Kbit SPI Serial EEPROM with 1024 × 8-bit organization, 16-byte page size, and 2.5–5.5 V supply range. It operates across -40°C to +125°C (Automotive E grade), supports up to 10 MHz clock, and delivers 1,000,000 erase/write cycles for nonvolatile data storage in automotive control modules.
For engineers reviewing the 25LC080AT-E/ST datasheet, 25LC080AT-E/ST pinout, 25LC080AT-E/ST application, or 25LC080AT-E/ST equivalent, key selection criteria include its TSSOP-8 package, hardware write-protection via WP pin, HOLD functionality for interrupt-safe SPI pauses, and automotive-grade temperature compliance.
Technical Context
The 25LC080AT-E/ST implements a standard SPI Mode 0,0 interface with separate SI/SO lines and CS-controlled device selection. Its internal architecture includes a status register with WIP, WEL, BP0/BP1, and WPEN bits enabling configurable block protection and write-enable state management.
It uses self-timed internal write cycles (max 5 ms), supports sequential read with automatic address incrementing, and features hardware-level data protection including power-on reset of the write enable latch, built-in write-protect circuitry, and ESD immunity exceeding 4 kV on all pins.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 8 Kbit (1024 × 8-bit) - fixed capacity for firmware parameter storage or calibration data retention |
| Page Size | 16 bytes - limits maximum contiguous write burst without crossing physical page boundaries |
| Max Clock Frequency | 10 MHz at VCC ≥ 4.5 V - enables high-speed SPI communication in automotive microcontroller interfaces |
| Write Cycle Time | 5 ms max - defines minimum interval between successive write operations affecting system latency |
| Endurance | 1,000,000 erase/write cycles - ensures long-term reliability in field-updatable systems |
| Data Retention | > 200 years - guarantees nonvolatile data integrity over full product lifecycle |
| Operating Temp | -40°C to +125°C - qualified for under-hood automotive applications per AEC-Q100 stress requirements |
| VCC Range | 2.5 V to 5.5 V - compatible with 3.3 V and 5 V logic domains without level shifting |
Pinout & Package
25LC080AT-E/ST is housed in an 8-lead TSSOP package (4.4 mm body width, 0.65 mm pitch), RoHS-compliant and Pb-free, optimized for space-constrained automotive PCB layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS (Pin 1) | Chip Select Input | Active-low enable signal; must be low for SPI transaction initiation and high to terminate write cycle and enter standby mode |
| SO (Pin 2) | Serial Data Output | Tri-state output delivering memory contents on falling edge of SCK during read operations |
| WP (Pin 3) | Write-Protect Pin | Hardware lock for Status Register writes when WPEN bit is set; grounded to enforce permanent protection |
| VSS (Pin 4) | Ground Reference | Primary return path for all internal circuits and I/O drivers; requires low-impedance connection to system GND plane |
| SI (Pin 5) | Serial Data Input | Latches instruction, address, and data on rising edge of SCK; supports MSB-first SPI protocol framing |
| SCK (Pin 6) | Serial Clock Input | Synchronizes all SPI transfers; timing constraints require min 50 ns high/low times at 10 MHz operation |
| HOLD (Pin 7) | Hold Input | Pauses ongoing SPI sequence without resetting state; must be asserted while SCK is low to avoid bus contention |
| VCC (Pin 8) | Supply Voltage | Power input supporting 2.5–5.5 V range; decoupling capacitor required within 10 mm of pin for noise immunity |
Key Features
| Feature | Design Value |
|---|---|
| Block Write Protection | Configurable via BP0/BP1 bits to protect none, 1/4, 1/2, or all memory - enables secure boot code partitioning |
| HOLD Functionality | Interrupt-safe SPI pause/resume without retransmission - critical for real-time MCU interrupt handling |
| Self-Timed Write Cycles | No external timing control needed; internal oscillator manages 5 ms erase/write - simplifies host firmware design |
| Power-On Data Protection | Write enable latch resets at power-up and after each write - prevents accidental corruption during brown-out |
| High Reliability | 1M endurance cycles and >200-year data retention - validated for 15+ year automotive service life |
| Pb-Free & RoHS Compliance | Meets EU Directive 2011/65/EU and JESD204B - supports global automotive manufacturing requirements |
Applications
| Engine Control Unit (ECU) Calibration Storage | Advanced Driver Assistance Systems (ADAS) Configuration |
|---|---|
Use Scenario: Storing trim values, sensor offsets, and adaptive learning parameters updated during vehicle operation. IC Role / Device Role / Timing Role: Nonvolatile parameter memory interfaced via SPI to 32-bit automotive MCU with real-time OS. Use Value: Enables field updates without requiring flash reprogramming; 125°C rating ensures stability near engine bay heat sources. | Use Scenario: Holding camera calibration matrices, radar beamforming coefficients, and lane detection thresholds. IC Role / Device Role / Timing Role: Dedicated configuration store accessed during ADAS module power-up and runtime recalibration. Use Value: Isolates critical safety-critical settings from main MCU flash, reducing update risk and enabling independent validation. |
| Body Control Module (BCM) User Preference Memory | Electric Power Steering (EPS) Fault Log Storage |
Use Scenario: Retaining seat/mirror position, climate presets, and lighting profiles across ignition cycles. IC Role / Device Role / Timing Role: Low-power SPI EEPROM accessed during BCM initialization and user input events. Use Value: 5 μA standby current minimizes battery drain; WP pin hardens against unintended writes during CAN bus noise events. | Use Scenario: Recording torque sensor anomalies, motor phase errors, and thermal shutdown events for diagnostic retrieval. IC Role / Device Role / Timing Role: Event-triggered logging device synchronized to EPS MCU's fault detection ISR. Use Value: 16-byte page writes allow efficient timestamped entry storage; HOLD pin preserves log integrity during MCU interrupts. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 25LC080AT-I/ST | Industrial temp range (-40°C to +85°C); identical electrical specs and pinout | Not qualified for under-hood automotive use; suitable for cabin electronics only | Select when operating environment stays below 85°C and AEC-Q100 qualification is not required |
| AT25080B-SSHL-B | Same 8 Kbit capacity, 16-byte page, but 2.5–5.5 V VCC and -40°C to +125°C rating; SPI-compatible but different status register layout | Requires firmware adaptation for status bit interpretation and write-protect behavior | Choose if sourcing diversification is prioritized and minor driver updates are acceptable |
Compared with 25LC080AT-E/ST, the 25LC080AT-I/ST lacks automotive temperature qualification but offers identical functionality at lower cost, while AT25080B-SSHL-B provides second-source availability with minor register-level integration effort.
Availability
25LC080AT-E/ST is available at Aetrix Electronics and suitable for automotive control units, ADAS subsystems, and body electronics requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 25LC080AT-E/ST includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog devices, and memory solutions, headquartered in Chandler, Arizona, serving automotive, industrial, and consumer markets globally.
The 25LC080A/B family was designed specifically for automotive-grade serial EEPROM applications requiring high reliability, extended temperature operation, and robust SPI interface compatibility with modern MCUs.
FAQ
What is the maximum SPI clock frequency supported by the 25LC080AT-E/ST?
The 25LC080AT-E/ST supports up to 10 MHz SPI clock frequency when VCC is 4.5 V to 5.5 V. At lower supply voltages (2.5 V ≤ VCC < 4.5 V), the maximum clock drops to 5 MHz, and at 1.8 V ≤ VCC < 2.5 V it is 3 MHz. These limits ensure reliable setup/hold timing margins per AC specifications in DS21808D.
Does the 25LC080AT-E/ST require external pull-up resistors on its SO or SI lines?
No, the 25LC080AT-E/ST does not require external pull-ups on SO or SI. Its SO pin is actively driven and tri-stated when deselected, and SI is a CMOS input with negligible leakage. Pull-ups may interfere with SPI bus sharing and are unnecessary per Microchip's recommended interface design in DS21808D.
How does the HOLD pin function during an active SPI read sequence on the 25LC080AT-E/ST?
During an active SPI read, asserting HOLD low places the 25LC080AT-E/ST into hold mode: SO goes high-impedance, and SI/SCK inputs are ignored except CS. The internal address pointer retains position. When HOLD is returned high while SCK is low, reading resumes from the same byte - enabling deterministic interrupt servicing without data loss.
Can the 25LC080AT-E/ST be used in a 1.8 V system?
No, the 25LC080AT-E/ST is not rated for 1.8 V operation. Its specified VCC range is 2.5 V to 5.5 V. For 1.8 V systems, Microchip's 25AA080A/B series (e.g., 25AA080AT-I/ST) supports 1.8–5.5 V and shares identical pinout and instruction set, but lacks automotive temperature qualification.
What happens if a page write crosses a 16-byte boundary on the 25LC080AT-E/ST?
If a page write command attempts to cross a 16-byte boundary, data wraps around to the start of the current page instead of advancing to the next page. This overwrites previously written bytes in that page. The 25LC080AT-E/ST does not auto-increment across pages - software must enforce alignment to prevent unintended corruption.
25LC080AT-E/ST Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 8Kbit
- Memory Organization:
- 1K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 10 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
25LC080AT-E/ST FAQ
1.How can I place an order for 25LC080AT-E/ST through Aetrix?
Please submit a Request for Quotation (RFQ) for 25LC080AT-E/ST on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 25LC080AT-E/ST reliable?
The price and inventory of 25LC080AT-E/ST are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 25LC080AT-E/ST is usually 5 days.
3.What payment methods are accepted for 25LC080AT-E/ST?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 25LC080AT-E/ST transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 25LC080AT-E/ST?
25LC080AT-E/ST orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 25LC080AT-E/ST order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 25LC080AT-E/ST?
For technical support, including 25LC080AT-E/ST datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 25LC080AT-E/ST requirements.
6.How does Aetrix verify that 25LC080AT-E/ST is sourced from the original manufacturer or authorized distributors?
All 25LC080AT-E/ST products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 25LC080AT-E/ST meets industry standards.
7.What is the process for return or replacement of 25LC080AT-E/ST?
All 25LC080AT-E/ST units undergo pre-shipment inspection (PSI). If there is an issue with 25LC080AT-E/ST, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 25LC080AT-E/ST part is unused and in its original packaging.
Return procedure for 25LC080AT-E/ST:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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