Microchip Technology 25LC128-I/MF
- Part No.:
- 25LC128-I/MF
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-VDFN Exposed Pad
- Datasheet:
-
25LC128-I/MF.pdf
- Description:
- IC EEPROM 128KBIT SPI 8DFN
- Quantity:
- Payment:

- Shipping:

Inventory:588
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Product details
Overview
25LC128-I/MF from Microchip Technology Inc. is a 128 Kbit SPI Serial EEPROM with 16,384 × 8-bit organization, 64-byte page size, and industrial temperature range (−40°C to +85°C). It operates at up to 10 MHz clock frequency, supports hardware write protection via WP pin, and delivers 5 µA standby current at 5.5V - used for nonvolatile configuration storage in microcontroller-based embedded systems.
For engineers reviewing the 25LC128-I/MF datasheet, 25LC128-I/MF pinout, 25LC128-I/MF application, or 25LC128-I/MF equivalent, key selection criteria include SPI interface timing compliance (TCSH/TCSS), VCC range (2.5V–5.5V), page-write endurance (1M cycles), and TSSOP-8 package compatibility with board-level space constraints.
Technical Context
The 25LC128-I/MF implements a standard SPI Mode 0,0 interface with separate SI/SO lines and active-low CS control. Its internal architecture includes a 64-byte page latch, STATUS register with BP0/BP1 block protection bits, and hardware write-enable logic gated by WREN/WRDI commands.
It features HOLD pin support for interrupt-safe transaction suspension, self-timed internal write cycles (≤5 ms), and dual-layer data protection: power-on reset of the write-enable latch plus dedicated WP pin functionality enabled only when WPEN bit is set in STATUS register.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 128 Kbit (16,384 × 8-bit) - provides sufficient nonvolatile storage for firmware parameters, calibration data, or device identity in resource-constrained MCUs. |
| Interface | SPI-compatible serial bus (Mode 0,0) - enables direct connection to PIC® and other MCU SPI peripherals without protocol translation. |
| Max Clock Frequency | 10 MHz at VCC ≥ 4.5V - supports high-speed read/write in systems requiring rapid configuration updates. |
| Page Size | 64 bytes - defines maximum contiguous write length; crossing page boundaries wraps data within same physical page. |
| Write Endurance | 1,000,000 erase/write cycles - ensures long-term reliability in applications with frequent parameter logging or field-upgrade operations. |
| Data Retention | >200 years - guarantees persistent storage integrity across product lifetime without refresh. |
| Supply Voltage | 2.5V to 5.5V - compatible with both 3.3V and 5V system rails, simplifying mixed-voltage board design. |
Pinout & Package
25LC128-I/MF is packaged in an 8-lead TSSOP (Thin Shrink Small Outline Package) with 0.65 mm pitch, body dimensions 4.4 mm × 3.0 mm × 1.2 mm, and exposed pad optional for thermal relief or grounding.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select Input | Active-low enable signal; deselecting forces SO into high-impedance state for multi-device SPI bus sharing. |
| SO | Serial Data Output | Outputs memory data on falling edge of SCK; tri-stated when CS is high or HOLD is asserted. |
| WP | Write-Protect Pin | Hardware lock for STATUS register nonvolatile bits when WPEN = 1; no effect if WPEN = 0. |
| VSS | Ground | Reference return path for all digital and internal charge-pump circuits; must be low-impedance. |
| SI | Serial Data Input | Accepts instructions, addresses, and write data on rising edge of SCK; latched synchronously. |
| SCK | Serial Clock Input | Master-generated clock; rising edge samples SI, falling edge updates SO; timing critical for AC specs. |
| HOLD | Hold Input | Pauses ongoing SPI transaction without resetting state; requires SCK low before assertion to activate. |
| VCC | Supply Voltage | Power input for core logic and EEPROM array; internal charge pump generates programming voltage. |
Key Features
| Feature | Design Value |
|---|---|
| Block Write Protection | Selectable protection of none / 1/4 / 1/2 / full memory array via BP0/BP1 bits - prevents accidental overwrites of critical firmware sections. |
| Self-Timed Write Cycle | Internal 5 ms max write completion - eliminates need for external timeout management; WIP bit indicates busy status. |
| Power-On Write Protection | Write-enable latch resets at power-up - prevents spurious writes during supply ramp-up or brown-out conditions. |
| HOLD Functionality | Interrupt-safe pause/resume of SPI sequences - allows host MCU to service higher-priority tasks without reinitializing communication. |
| ESD Robustness | >4000V HBM - enhances reliability in handling-sensitive industrial and automotive assembly environments. |
Applications
| Industrial Sensor Node | Medical Device Calibration |
|---|---|
Use Scenario: Storing sensor offset/gain coefficients and operational history in battery-powered wireless nodes. IC Role / Device Role / Timing Role: Nonvolatile configuration storage with infrequent writes and frequent reads over SPI interface. Use Value: 1M endurance and >200-year retention ensure calibration data survives entire product lifecycle without degradation. |
Use Scenario: Holding FDA-mandated calibration records and usage logs in portable diagnostic equipment. IC Role / Device Role / Timing Role: Secure, tamper-resistant parameter storage with hardware write-lock capability. Use Value: WP pin + WPEN bit enables irreversible lock of regulatory-critical data after factory calibration. |
| Automotive Body Control Module | Consumer Appliance Settings |
Use Scenario: Saving user preferences and fault codes in AEC-Q100 qualified vehicle subsystems. IC Role / Device Role / Timing Role: Industrial-temp EEPROM interfacing with CAN-connected MCU via SPI. Use Value: −40°C to +85°C operation and 5 µA standby current meet automotive low-power requirements. |
Use Scenario: Retaining cooking programs, display language, and safety thresholds in smart ovens and washers. IC Role / Device Role / Timing Role: Low-cost, reliable nonvolatile memory for consumer-grade MCU firmware extensions. Use Value: 2.5V–5.5V VCC range matches common appliance 3.3V/5V rails; TSSOP-8 footprint minimizes PCB area. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 25AA128-I/MF | Wider VCC range (1.8V–5.5V); supports lower-voltage operation down to 1.8V. | Better suited for battery-powered or ultra-low-power designs where 2.5V minimum is not guaranteed. | Select when system VCC may dip below 2.5V; otherwise 25LC128-I/MF offers identical feature set at same price point. |
| AT25DF041A-MAU-T | 4 Mbit density, quad SPI interface, faster 50 MHz clock; no HOLD pin; different instruction set. | Targets high-speed firmware storage, not parameter/configuration storage; requires driver rewrite. | Choose only if migrating to larger capacity or quad-SPI infrastructure; not drop-in compatible with 25LC128-I/MF. |
Compared with 25AA128-I/MF and AT25DF041A-MAU-T, the 25LC128-I/MF balances industrial temperature support, proven SPI compatibility, and cost-effective 128 Kbit density - making it optimal for configuration storage where pin count, code reuse, and qualification stability outweigh raw speed or capacity needs.
Availability
25LC128-I/MF is available at Aetrix Electronics and suitable for industrial sensor nodes, medical device calibration, and automotive body control modules requiring stable component supply and long-term obsolescence planning.
Supply support for 25LC128-I/MF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog components, and memory solutions, headquartered in Chandler, Arizona, with global manufacturing and support infrastructure.
The 25LC128-I/MF belongs to Microchip's legacy SPI EEPROM product line, designed specifically for robust, low-power, nonvolatile data storage in embedded systems where reliability and qualification (AEC-Q100, RoHS) are mandatory.
FAQ
What is the operating voltage range for the 25LC128-I/MF?
The 25LC128-I/MF operates from 2.5V to 5.5V. This range ensures compatibility with both 3.3V and 5V logic systems. Operation below 2.5V is not guaranteed - unlike the 25AA128 variant, which supports down to 1.8V. The 25LC128-I/MF maintains full AC and DC specifications across its rated VCC window, including 10 MHz clock support at 4.5–5.5V.
Does the 25LC128-I/MF support page writes, and what is the maximum page size?
Yes, the 25LC128-I/MF supports page writes with a fixed 64-byte page size. Up to 64 bytes can be loaded into the page buffer before initiating an internal write cycle. Attempting to write across a page boundary causes wraparound within the same page - software must enforce alignment. Each page write completes in ≤5 ms, and the WIP bit in the STATUS register indicates ongoing activity.
How does hardware write protection work on the 25LC128-I/MF?
Hardware write protection on the 25LC128-I/MF requires both the WPEN bit (bit 7 of STATUS register) to be set to '1' and the WP pin (pin 3) held low. When enabled, this blocks writes to nonvolatile STATUS register bits only - all memory array operations remain functional. If WPEN = 0, the WP pin has no effect, allowing full STATUS register programmability regardless of WP pin state.
What package type is used for the 25LC128-I/MF part number suffix '/MF'?
The '/MF' suffix denotes the 8-lead TSSOP (Thin Shrink Small Outline Package) variant of the 25LC128-I/MF. It measures 4.4 mm × 3.0 mm × 1.2 mm with 0.65 mm lead pitch and includes an exposed pad (optional connection to VSS or floating). This package is RoHS-compliant and optimized for automated surface-mount assembly in space-constrained industrial PCBs.
Is the 25LC128-I/MF qualified for automotive applications?
No - the 25LC128-I/MF carries the 'I' (Industrial) temperature grade (−40°C to +85°C) and is not AEC-Q100 qualified. While the 25LC128 family includes AEC-Q100 qualified variants (e.g., 25LC128-E/MF for Extended temp), the 'I' suffix explicitly denotes industrial qualification only. For automotive use, engineers must select a part number with 'E' or explicit AEC-Q100 marking per Microchip's device selection table.
25LC128-I/MF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-VDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 128Kbit
- Memory Organization:
- 16K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 10 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-DFN-S (6x5)
25LC128-I/MF FAQ
1.How can I place an order for 25LC128-I/MF through Aetrix?
Please submit a Request for Quotation (RFQ) for 25LC128-I/MF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 25LC128-I/MF reliable?
The price and inventory of 25LC128-I/MF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 25LC128-I/MF is usually 5 days.
3.What payment methods are accepted for 25LC128-I/MF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 25LC128-I/MF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 25LC128-I/MF?
25LC128-I/MF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 25LC128-I/MF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 25LC128-I/MF?
For technical support, including 25LC128-I/MF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 25LC128-I/MF requirements.
6.How does Aetrix verify that 25LC128-I/MF is sourced from the original manufacturer or authorized distributors?
All 25LC128-I/MF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 25LC128-I/MF meets industry standards.
7.What is the process for return or replacement of 25LC128-I/MF?
All 25LC128-I/MF units undergo pre-shipment inspection (PSI). If there is an issue with 25LC128-I/MF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 25LC128-I/MF part is unused and in its original packaging.
Return procedure for 25LC128-I/MF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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