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Microchip Technology 25LC128-I/ST
- Part No.:
- 25LC128-I/ST
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
25LC128-I/ST.pdf
- Description:
- IC EEPROM 128KBIT SPI 8TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:155
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Product details
Overview
25LC128-I/ST from Microchip Technology Inc. is a 128 Kbit SPI Serial EEPROM with 16,384 × 8-bit organization, 64-byte page size, and industrial temperature range (−40°C to +85°C). It operates at up to 10 MHz clock frequency with 5 mA read/write current at 5.5 V and features hardware write protection via WP pin and STATUS register control. It is used in microcontroller-based systems for nonvolatile parameter storage, calibration data retention, and firmware configuration.
For engineers reviewing the 25LC128-I/ST datasheet, 25LC128-I/ST pinout, 25LC128-I/ST application, or 25LC128-I/ST equivalent, key selection considerations include its 2.5V–5.5V supply range, TSSOP-8 package compatibility, SPI Mode 0/0 and Mode 1/1 support, HOLD functionality for interrupt-safe bus arbitration, and block-level write protection (none/¼/½/all array).
Technical Context
The 25LC128-I/ST implements a standard SPI-compatible serial interface with separate SI (data in), SO (data out), SCK (clock), CS (chip select), WP (write-protect), and HOLD (bus pause) signals. It uses CMOS technology with internal high-voltage generation for EEPROM programming and supports both byte and page write operations within 64-byte boundaries.
Its functional architecture includes an 8-bit instruction register, auto-incrementing address pointer for sequential reads, WIP/WEL bits in a nonvolatile STATUS register, and programmable block protection (BP0/BP1) enabling selective write-lock of memory segments. The device resets its write enable latch on power-up, WRDI, WRSR, or WRITE completion.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 128 Kbit (16,384 × 8-bit), sufficient for storing boot configuration, sensor calibration tables, or device identity data in space-constrained embedded designs. |
| Interface | SPI-compatible serial bus (Mode 0,0 and Mode 1,1), enabling direct connection to PIC® and other MCU SPI peripherals without protocol translation logic. |
| Max Clock Frequency | 10 MHz at VCC ≥ 4.5 V, allowing fast read/write cycles in high-throughput applications such as real-time logging or dynamic parameter updates. |
| Page Size | 64 bytes, defining the maximum contiguous data that can be written in a single page write command - critical for minimizing write latency and wear leveling efficiency. |
| Write Endurance | 1,000,000 erase/write cycles per address, supporting long-life operation in field-upgradable devices like industrial controllers or medical instruments. |
| Data Retention | >200 years at +25°C, ensuring reliable storage of critical settings across product lifecycles without refresh requirements. |
| Operating Voltage | 2.5 V to 5.5 V, compatible with both 3.3 V and 5 V logic domains and simplifying integration into mixed-supply systems. |
| Temperature Range | Industrial grade: −40°C to +85°C, validated for use in automotive body electronics, factory automation, and outdoor IoT gateways. |
Pinout & Package
25LC128-I/ST is packaged in an 8-lead TSSOP (Thin Shrink Small Outline Package) with 0.65 mm pitch, JEDEC MO-153 compliant, and marked "25LC128I/ST" with date code and traceability. The exposed pad is not electrically connected and may be left floating or tied to VSS for thermal enhancement.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (CS) | Chip Select Input | Active-low enable signal; must be low for all SPI transactions; drives SO to high-impedance when high to allow multi-device bus sharing. |
| 2 (SO) | Serial Data Output | Tri-state output delivering read data MSB-first on falling edge of SCK; enters high-Z state when CS is high or HOLD is asserted. |
| 3 (WP) | Write-Protect Pin | Hardware lock for STATUS register nonvolatile bits when WPEN = 1; low = protection enabled; high = full write access including BP0/BP1 configuration. |
| 4 (VSS) | Ground | Reference return path for all digital and internal charge-pump circuits; requires low-impedance PCB connection to minimize noise coupling during write cycles. |
| 5 (SI) | Serial Data Input | Accepts instructions, addresses, and write data MSB-first on rising edge of SCK; sampled only when CS is low and HOLD is high. |
| 6 (SCK) | Serial Clock Input | Master-generated clock synchronizing all SPI transfers; rising edge latches SI, falling edge updates SO; timing constraints vary by VCC level. |
| 7 (HOLD) | Hold Input | Pauses ongoing SPI sequence without reset; must be driven low while SCK is low to activate; tri-states SI/SO/SCK during hold for safe interrupt servicing. |
| 8 (VCC) | Supply Voltage | Primary power input (2.5–5.5 V); powers internal logic, EEPROM array, and HV generator; requires local 0.1 µF ceramic decoupling near the pin. |
Key Features
| Feature | Design Value |
|---|---|
| Self-timed write cycle | Internal 5 ms max write completion time eliminates need for external timeout logic or polling overhead in host firmware. |
| Block write protection | Configurable via STATUS register (BP0/BP1) to protect none, upper 1/4, upper 1/2, or entire 128 Kbit array - prevents accidental overwrites of critical firmware or calibration data. |
| HOLD function | Enables deterministic bus arbitration: host can suspend EEPROM communication mid-transfer to service higher-priority interrupts and resume from exact point without retransmission. |
| Power-on write disable | Write enable latch resets at power-up, preventing spurious writes during brown-out or unstable supply conditions - enhances system robustness in uncontrolled power environments. |
| ESD protection | >4 kV HBM rating on all pins ensures reliability during board handling, assembly, and field deployment in electrostatic-prone industrial settings. |
| RoHS & AEC-Q100 qualified | Complies with automotive-grade stress testing (AEC-Q100 Rev G Grade 3), validating suitability for under-hood and chassis-mounted ECUs requiring extended temperature and lifetime reliability. |
Applications
| Industrial PLC Configuration Storage | Automotive Body Control Module (BCM) |
|---|---|
Use Scenario: Storing I/O mapping, PID tuning parameters, and alarm thresholds in programmable logic controllers deployed in factory automation lines. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed via SPI during boot and runtime updates; HOLD enables seamless parameter reload during motion-control interrupt events. Use Value: Eliminates need for battery-backed SRAM; 1M endurance supports decades of field recalibration; block protection prevents corruption of safety-critical settings during firmware updates. |
Use Scenario: Retaining door lock states, mirror position presets, and lighting profiles in automotive BCMs operating across −40°C to +85°C ambient. IC Role / Device Role / Timing Role: AEC-Q100 qualified EEPROM interfacing directly with 3.3 V MCU SPI port; WP pin hardwired to ground for permanent protection of factory-set configuration blocks. Use Value: >200-year data retention ensures settings survive vehicle lifetime; 2.5–5.5 V operation accommodates wide automotive battery voltage swings; TSSOP-8 footprint minimizes PCB area in space-constrained modules. |
| Medical Infusion Pump Calibration | Smart Energy Meter Firmware Settings |
Use Scenario: Storing flow-rate calibration coefficients, dose history logs, and user-defined therapy profiles in Class II medical infusion pumps requiring regulatory traceability. IC Role / Device Role / Timing Role: Secure, tamper-resistant memory with write-protection enforced by both WP pin and STATUS register; RDSR polling confirms WIP status before critical delivery commands. Use Value: 1M write cycles enable full audit trail logging over device lifetime; ESD immunity >4 kV meets IEC 60601-1 ESD requirements; industrial temp grade supports sterilization and storage environments. |
Use Scenario: Holding tariff schedules, meter ID, phase calibration offsets, and security keys in ANSI C12.22-compliant smart meters installed in utility substations and residential panels. IC Role / Device Role / Timing Role: SPI EEPROM integrated into meter SoC subsystem; page-write capability allows efficient bulk update of time-of-use rate tables during OTA firmware upgrades. Use Value: Block protection isolates security keys from firmware update routines; 5 µA standby current extends battery backup life during grid outages; RoHS compliance meets global utility procurement mandates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 25AA128-I/ST | Wider VCC range (1.8–5.5 V); supports lower-voltage 1.8 V systems where 25LC128-I/ST cannot operate. | Preferred in ultra-low-power portable devices or mixed-voltage MCUs with 1.8 V I/O domains. | Select when system VCC may drop below 2.5 V or when interoperability with 1.8 V logic is required. |
| AT25128B-SSHL-T | Same 128 Kbit density and TSSOP-8 package; 20 MHz max clock (at 5 V); built-in write-cycle inhibit during power transitions. | Better suited for high-speed logging or applications requiring faster write throughput and enhanced brown-out immunity. | Choose when clock speed >10 MHz is needed or when additional power-fail write abort functionality is critical. |
Compared with 25AA128-I/ST and AT25128B-SSHL-T, the 25LC128-I/ST offers optimal balance of industrial temperature validation, proven AEC-Q100 qualification, and cost-effective integration in 3.3 V/5 V embedded systems where 1.8 V operation is unnecessary and 10 MHz bandwidth suffices.
Availability
25LC128-I/ST is available at Aetrix Electronics and suitable for industrial automation, automotive electronics, and medical instrumentation requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for 25LC128-I/ST includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog components, and memory solutions, headquartered in Chandler, Arizona, with global design, manufacturing, and sales operations.
The 25LC128 belongs to Microchip's serial EEPROM product line, designed specifically for reliable, low-pin-count nonvolatile storage in resource-constrained embedded systems requiring SPI interface simplicity, industrial-grade reliability, and long-term data integrity.
FAQ
What is the maximum clock frequency supported by the 25LC128-I/ST?
The 25LC128-I/ST supports up to 10 MHz clock frequency when VCC is 4.5 V to 5.5 V. At 2.5 V ≤ VCC < 4.5 V, the maximum clock drops to 5 MHz, and at 1.8 V ≤ VCC < 2.5 V it is limited to 3 MHz. These limits ensure reliable setup/hold timing across voltage and temperature ranges, and are specified in Table 1-2 of the DS20001831F datasheet. The 25LC128-I/ST does not support 10 MHz operation below 4.5 V.
Does the 25LC128-I/ST require external pull-up resistors on its SPI lines?
No, the 25LC128-I/ST does not require external pull-ups on SI, SO, or SCK - these pins are actively driven. However, CS and WP are active-low inputs with internal weak pull-ups disabled by default; external pull-ups (typically 4.7 kΩ to VCC) are recommended on CS for noise immunity in noisy environments, and on WP if hardware write protection is desired but not permanently asserted. The 25LC128-I/ST datasheet specifies no internal pull-ups on these control pins.
How does the HOLD function work on the 25LC128-I/ST during an ongoing read or write sequence?
The HOLD function on the 25LC128-I/ST suspends SPI communication mid-sequence when HOLD is pulled low while SCK is low. During hold, SI, SO, and SCK enter high-impedance states and all input transitions (except CS) are ignored. Communication resumes from the exact bit position when HOLD is returned high while SCK remains low. This allows the host MCU to service time-critical interrupts without losing transaction context - a feature explicitly implemented in the 25LC128-I/ST's silicon design.
Can the 25LC128-I/ST be used in automotive applications?
Yes, the 25LC128-I/ST is AEC-Q100 qualified (Grade 3) and rated for −40°C to +85°C operation, making it suitable for automotive body electronics, infotainment subsystems, and chassis control modules. Its RoHS compliance, 1,000,000 write endurance, and >200-year data retention meet stringent automotive reliability requirements. The "I" suffix in 25LC128-I/ST denotes Industrial temperature grade, which overlaps with AEC-Q100 Grade 3 specifications.
What is the purpose of the WP pin on the 25LC128-I/ST, and how does it interact with the STATUS register?
The WP pin on the 25LC128-I/ST provides hardware-level write protection for the nonvolatile bits in the STATUS register (BP0, BP1, WPEN) when the WPEN bit is set high. If WP is low and WPEN = 1, writes to those bits are blocked; all other operations proceed normally. If WPEN = 0, the WP pin has no effect. This dual-layer protection - configurable via software (WRSR) and enforceable via hardware (WP) - ensures robust safeguarding of memory protection settings in the 25LC128-I/ST.
25LC128-I/ST Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 128Kbit
- Memory Organization:
- 16K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 10 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
25LC128-I/ST FAQ
1.How can I place an order for 25LC128-I/ST through Aetrix?
Please submit a Request for Quotation (RFQ) for 25LC128-I/ST on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 25LC128-I/ST reliable?
The price and inventory of 25LC128-I/ST are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 25LC128-I/ST is usually 5 days.
3.What payment methods are accepted for 25LC128-I/ST?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 25LC128-I/ST transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 25LC128-I/ST?
25LC128-I/ST orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 25LC128-I/ST order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 25LC128-I/ST?
For technical support, including 25LC128-I/ST datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 25LC128-I/ST requirements.
6.How does Aetrix verify that 25LC128-I/ST is sourced from the original manufacturer or authorized distributors?
All 25LC128-I/ST products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 25LC128-I/ST meets industry standards.
7.What is the process for return or replacement of 25LC128-I/ST?
All 25LC128-I/ST units undergo pre-shipment inspection (PSI). If there is an issue with 25LC128-I/ST, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 25LC128-I/ST part is unused and in its original packaging.
Return procedure for 25LC128-I/ST:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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