My Inquiry
My Account
Microchip Technology 25LC128T-E/ST
- Part No.:
- 25LC128T-E/ST
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
25LC128T-E/ST.pdf
- Description:
- IC EEPROM 128KBIT SPI 8TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:1,139
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
25LC128T-E/ST from Microchip Technology Inc. is a 128 Kbit SPI Serial EEPROM with 16,384 × 8-bit organization, 64-byte page size, and 10 MHz max clock frequency at 4.5–5.5 V. It features hardware write protection via WP pin, HOLD suspend functionality, and operates across –40°C to +125°C for extended-temperature automotive and industrial control applications.
For engineers reviewing the 25LC128T-E/ST datasheet, 25LC128T-E/ST pinout, 25LC128T-E/ST application, or 25LC128T-E/ST equivalent, this page delivers verified electrical specs, TSSOP-8 package mapping, SPI timing constraints, endurance (1M cycles), data retention (>200 years), and real-world use cases in firmware storage, calibration data logging, and configuration memory for microcontroller-based systems.
Technical Context
The 25LC128T-E/ST implements a standard SPI Mode 0,0 interface with separate SI (data-in) and SO (data-out) lines, requiring CS, SCK, and optional HOLD/WP control. Its internal architecture includes a 64-byte page latch, status register with WIP/WEL/BP0/BP1 bits, and high-voltage generator for EEPROM programming.
It supports byte-write and page-write operations with self-timed internal write cycles (≤5 ms), automatic address roll-over during sequential reads, and programmable block protection covering none, 1/4, 1/2, or all of the 128 Kbit array. Power-on reset clears the write enable latch, and hardware write protection engages only when WPEN=1 and WP=low.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 128 Kbit (16,384 × 8-bit), sufficient for firmware boot code, device calibration tables, or parameter sets in resource-constrained embedded systems. |
| Interface | SPI-compatible serial bus (Mode 0,0), enabling direct connection to PIC® and other MCU SPI peripherals without glue logic. |
| Max Clock Frequency | 10 MHz at VCC = 4.5–5.5 V; reduces to 5 MHz at 2.5–4.5 V - defines maximum throughput (up to 1.25 MB/s theoretical read rate). |
| Write Endurance | 1,000,000 erase/write cycles per address - supports frequent field-updatable configuration storage in industrial controllers. |
| Data Retention | >200 years at 25°C - ensures long-term reliability for unattended equipment like smart meters or remote sensors. |
| Operating Temperature | –40°C to +125°C (Extended grade E), qualified to AEC-Q100 - validated for under-hood automotive ECUs and high-temp industrial PLC modules. |
| Supply Voltage Range | 2.5 V to 5.5 V - compatible with both 3.3 V and 5 V logic domains, simplifying mixed-voltage board design. |
Pinout & Package
25LC128T-E/ST is packaged in an 8-lead TSSOP (Thin Shrink Small Outline Package) with 0.65 mm pitch, JEDEC MO-153 compliant, and marked "25LC128I" or "25LC128E" depending on temperature grade. Pin 1 is located at the top-left corner with a beveled edge indicator.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (CS) | Chip Select Input | Active-low enable signal; must be low for all SPI transactions; rising edge initiates internal write cycle after valid command sequence. |
| 2 (SO) | Serial Data Output | Tri-state open-drain output; shifts out read data on falling SCK edge; enters high-Z when CS is high to share SPI bus. |
| 3 (WP) | Write-Protect Input | Hardware lock: disables STATUS register writes when WPEN=1 and WP=low; no effect on array reads or non-STATUS writes. |
| 4 (VSS) | Ground Reference | Primary return path for all internal circuitry; must be connected directly to system ground plane for noise immunity. |
| 5 (SI) | Serial Data Input | Latches instruction, address, and write data on rising SCK edge; requires setup/hold timing compliance per AC table. |
| 6 (SCK) | Serial Clock Input | Master-generated clock synchronizing all SPI transfers; rise/fall times ≤100 ns required for 10 MHz operation. |
| 7 (HOLD) | Hold Input | Suspends ongoing SPI transfer without resetting state; must be asserted while SCK is low to avoid bus contention. |
| 8 (VCC) | Supply Voltage | 2.5–5.5 V power input; bypass capacitor (0.1 µF ceramic) required within 10 mm of pin for stable read/write margins. |
Key Features
| Feature | Design Value |
|---|---|
| 64-byte page write buffer | Enables burst programming of up to 64 contiguous bytes per write cycle, reducing total write time vs. byte-by-byte writes. |
| Block write protection (BP0/BP1) | Configurable via STATUS register to protect 0%, 25%, 50%, or 100% of memory - prevents accidental overwrite of critical boot or calibration sectors. |
| HOLD pin suspend function | Pauses active SPI communication mid-sequence, allowing host MCU to service higher-priority interrupts without losing transaction context. |
| Power-on data protection | Automatic write-disable latch reset at power-up, plus built-in voltage monitoring, prevents corruption during brown-out or startup transients. |
| AEC-Q100 qualified (Grade 1) | Validated for automotive applications including engine control, body electronics, and ADAS subsystems operating at 125°C ambient. |
Applications
| Automotive Engine Control Unit (ECU) | Industrial Programmable Logic Controller (PLC) |
|---|---|
Use Scenario: Storing adaptive fuel trim tables and emission calibration parameters that must survive vehicle ignition cycles and thermal cycling. IC Role / Device Role / Timing Role: Nonvolatile configuration memory interfaced via SPI to main MCU; accessed during boot and runtime re-calibration. Use Value: 1M endurance and >200-year data retention ensure calibration integrity over full vehicle lifetime; E-grade temp range matches under-hood requirements. |
Use Scenario: Holding I/O module configuration, ladder logic firmware updates, and alarm history logs in factory automation systems. IC Role / Device Role / Timing Role: SPI-connected persistent storage for user-defined operational parameters and event timestamps. Use Value: Hardware WP pin prevents unauthorized firmware modification; HOLD function allows deterministic interrupt response during configuration writes. |
| Medical Infusion Pump | Smart Energy Meter |
Use Scenario: Recording dose history, error logs, and safety-critical calibration offsets in battery-powered portable devices requiring long-term reliability. IC Role / Device Role / Timing Role: Low-power EEPROM storing audit trail and sensor offset data; accessed infrequently but with guaranteed write completion. Use Value: 5 µA standby current extends battery life; self-timed 5 ms write cycle enables predictable power budgeting during data commits. |
Use Scenario: Storing tariff schedules, metering registers, and tamper-detection flags in utility-grade electricity meters deployed outdoors. IC Role / Device Role / Timing Role: Secure, temperature-stable memory for regulatory-compliant energy usage records and firmware version tracking. Use Value: AEC-Q100 qualification ensures performance at –40°C to +125°C ambient; ESD protection >4 kV withstands field handling stress. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 25AA128T-I/ST | Wider VCC range (1.8–5.5 V); supports 3 MHz operation down to 1.8 V; same pinout and instruction set. | Better suited for ultra-low-voltage battery-powered designs where 2.5 V minimum cannot be guaranteed. | Select 25AA128T-I/ST if system operates below 2.5 V; otherwise 25LC128T-E/ST offers superior high-temp reliability. |
| AT25DF041A-SSH-T | 4 Mbit density, quad-SPI support, faster 50 MHz clock; different instruction set and no HOLD pin. | Targeted at high-speed firmware storage (e.g., XIP boot code), not small-parameter EEPROM replacement. | Not drop-in; requires firmware rework for SPI mode and command translation; choose only for bandwidth-critical upgrades. |
Compared with 25AA128T-I/ST, the 25LC128T-E/ST trades lower-voltage flexibility for extended-temperature robustness and automotive qualification; versus AT25DF041A-SSH-T, it provides simpler SPI compatibility and proven reliability in low-density, high-reliability parameter storage roles.
Availability
25LC128T-E/ST is available at Aetrix Electronics and suitable for automotive ECU firmware storage, industrial PLC configuration backup, and medical device calibration logging requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 25LC128T-E/ST includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog components, and memory solutions, headquartered in Chandler, Arizona, with global manufacturing and support infrastructure.
The 25LC128T-E/ST belongs to Microchip's 25XX128 family of SPI EEPROMs, designed specifically for reliable, low-power, nonvolatile data storage in automotive, industrial, and medical systems demanding AEC-Q100 compliance and extended temperature operation.
FAQ
What is the maximum clock frequency supported by the 25LC128T-E/ST?
The 25LC128T-E/ST supports up to 10 MHz clock frequency when VCC is between 4.5 V and 5.5 V. At lower supply voltages (2.5–4.5 V), the maximum clock drops to 5 MHz, and operation below 2.5 V is not supported. This ensures timing margin compliance across its specified 2.5–5.5 V operating range and extended temperature grade.
Does the 25LC128T-E/ST require external pull-up resistors on its SPI lines?
The 25LC128T-E/ST SO pin is open-drain and requires an external pull-up resistor (typically 4.7 kΩ) to VCC for proper logic-high level establishment. CS, SI, SCK, WP, and HOLD are CMOS inputs and do not require pull-ups unless system-level noise immunity or default-state assurance dictates them - the 25LC128T-E/ST itself does not mandate them.
How does the HOLD pin function during an active SPI transaction on the 25LC128T-E/ST?
The HOLD pin on the 25LC128T-E/ST suspends ongoing SPI communication without resetting the internal state. When pulled low while SCK is low, SI/SO/SCK enter high-impedance and are ignored until HOLD returns high - allowing the host MCU to service interrupts and resume exactly where the transaction left off. The 25LC128T-E/ST remains selected throughout.
Can the 25LC128T-E/ST be used as a direct replacement for the 25AA128T-I/ST?
No - the 25LC128T-E/ST is not a direct replacement for the 25AA128T-I/ST due to differing VCC ranges (2.5–5.5 V vs. 1.8–5.5 V) and temperature grades (–40°C to +125°C vs. –40°C to +85°C). While pinout and instruction set are identical, the 25LC128T-E/ST lacks 1.8 V operation and adds AEC-Q100 qualification, making substitution conditional on voltage and environmental requirements.
What is the purpose of the WPEN bit in the STATUS register of the 25LC128T-E/ST?
The WPEN (Write-Protect Enable) bit in the 25LC128T-E/ST STATUS register controls whether the WP pin actively enforces hardware write protection. When WPEN = 1 and WP = low, writes to nonvolatile STATUS bits are disabled; when WPEN = 0, the WP pin is ignored entirely. This allows safe installation in systems with grounded WP pins while retaining full STATUS register configurability.
25LC128T-E/ST Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 128Kbit
- Memory Organization:
- 16K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 10 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
25LC128T-E/ST FAQ
1.How can I place an order for 25LC128T-E/ST through Aetrix?
Please submit a Request for Quotation (RFQ) for 25LC128T-E/ST on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 25LC128T-E/ST reliable?
The price and inventory of 25LC128T-E/ST are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 25LC128T-E/ST is usually 5 days.
3.What payment methods are accepted for 25LC128T-E/ST?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 25LC128T-E/ST transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 25LC128T-E/ST?
25LC128T-E/ST orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 25LC128T-E/ST order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 25LC128T-E/ST?
For technical support, including 25LC128T-E/ST datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 25LC128T-E/ST requirements.
6.How does Aetrix verify that 25LC128T-E/ST is sourced from the original manufacturer or authorized distributors?
All 25LC128T-E/ST products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 25LC128T-E/ST meets industry standards.
7.What is the process for return or replacement of 25LC128T-E/ST?
All 25LC128T-E/ST units undergo pre-shipment inspection (PSI). If there is an issue with 25LC128T-E/ST, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 25LC128T-E/ST part is unused and in its original packaging.
Return procedure for 25LC128T-E/ST:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
25LC128T-E/ST Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
