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Microchip Technology 25LC128T-I/ST
- Part No.:
- 25LC128T-I/ST
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
25LC128T-I/ST.pdf
- Description:
- IC EEPROM 128KBIT SPI 8TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:4,539
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Product details
Overview
25LC128T-I/ST from Microchip Technology Inc. is a 128 Kbit SPI Serial EEPROM with 16,384 × 8-bit organization, 64-byte page size, and industrial temperature range (–40°C to +85°C). It operates at up to 10 MHz clock frequency with 5 mA read/write current at 5.5 V and supports hardware write protection via WP pin and STATUS register. It is used in microcontroller-based systems for nonvolatile parameter storage, calibration data retention, and firmware configuration.
For engineers reviewing the 25LC128T-I/ST datasheet, 25LC128T-I/ST pinout, 25LC128T-I/ST application, or 25LC128T-I/ST equivalent, this page provides verified electrical specs, SPI timing constraints, HOLD/CS/WP functional behavior, package-specific pin mapping for TSSOP-8, and real-world use cases in embedded control and sensor modules.
Technical Context
The 25LC128T-I/ST implements a standard SPI Mode 0,0 interface with separate SI (data-in) and SO (data-out) lines, requiring CS low and HOLD high for active operation. Its internal architecture includes an 8-bit instruction register, page latches, and HV generator for EEPROM programming - all controlled by WREN/WRSR/RDSR command set.
It supports sequential read, byte/page write (max 64 bytes per page), self-timed internal write cycles (≤5 ms), and configurable block protection (none/1/4/1/2/all array). Write enable latch reset occurs on power-up, WRDI, WRSR, or successful WRITE - ensuring robust data integrity during brownout or interrupt service.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 128 Kbit (16,384 × 8-bit), sufficient for storing bootloader config, device ID, or sensor calibration tables |
| Interface | SPI-compatible serial bus (Mode 0,0), enabling direct connection to PIC® and other MCU SPI peripherals without glue logic |
| Max Clock Frequency | 10 MHz at VCC ≥ 4.5 V; drops to 5 MHz at 2.5–4.5 V - defines maximum data throughput in host-controlled transfers |
| Page Size | 64 bytes - constrains burst write length and requires software boundary checking to avoid wraparound corruption |
| Write Endurance | 1,000,000 erase/write cycles - supports frequent field updates in telemetry or logging applications |
| Data Retention | >200 years at 25°C - ensures long-term reliability for unattended industrial deployments |
| VCC Range | 2.5 V to 5.5 V - compatible with both 3.3 V and 5 V logic domains without level shifting |
Pinout & Package
25LC128T-I/ST is packaged in an 8-lead TSSOP (Thin Shrink Small Outline Package) with 0.65 mm pitch, JEDEC MO-153 compliant, and marked "25LC128I/ST" on top surface. Pin 1 is located at bottom-left corner when notch faces up.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (CS) | Chip Select Input | Active-low enable; deselects device and forces SO into high-impedance state to share SPI bus |
| 2 (SO) | Serial Data Output | Tri-state output delivering memory contents on falling edge of SCK; high-Z when CS high or HOLD asserted |
| 3 (WP) | Write-Protect Input | Hardware lock for STATUS register when WPEN=1; no effect on array writes unless enabled in STATUS |
| 4 (VSS) | Ground Reference | Primary return path for all internal circuits; must be low-impedance to minimize noise coupling into EEPROM core |
| 5 (SI) | Serial Data Input | Latches instructions, addresses, and data on rising edge of SCK; requires clean setup/hold timing per AC table |
| 6 (SCK) | Serial Clock Input | Synchronizes all SPI transactions; rise/fall times ≤100 ns required for 10 MHz operation |
| 7 (HOLD) | Hold Input | Pauses ongoing SPI sequence without resetting address pointer; must be driven low while SCK is low |
| 8 (VCC) | Supply Voltage | Power input (2.5–5.5 V); internal regulation enables stable EEPROM programming across voltage range |
Key Features
| Feature | Design Value |
|---|---|
| Block Write Protection | Selectable via BP1/BP0 bits: protect none, upper 1/4 (3000h–3FFFh), upper 1/2 (2000h–3FFFh), or entire array (0000h–3FFFh) |
| HOLD Functionality | Enables interrupt servicing mid-transaction; preserves internal address pointer and avoids reinitialization overhead |
| Power-On Write Disable | Write enable latch resets at power-up, preventing accidental writes during supply ramp-up or brownout recovery |
| ESD Robustness | >4 kV HBM - withstands handling and board-level ESD events common in industrial assembly environments |
| RoHS & AEC-Q100 | Compliant with RoHS Directive 2011/65/EU and qualified to AEC-Q100 Grade 2 (–40°C to +105°C ambient) for automotive subsystems |
Applications
| Industrial PLC Configuration Storage | Automotive Sensor Calibration |
|---|---|
|
Use Scenario: Storing I/O mapping, PID tuning parameters, and alarm thresholds in programmable logic controllers deployed in factory automation. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed via SPI during boot and runtime updates; retains values across power cycles. Use Value: Enables field-reprogrammable control logic without requiring flash reprogramming or external backup batteries. |
Use Scenario: Recording temperature-compensated offset/gain coefficients for pressure sensors in engine management systems. IC Role / Device Role / Timing Role: Calibration data repository written once during end-of-line test and read at startup; accessed via SPI under MCU control. Use Value: Achieves ±0.1% measurement accuracy over –40°C to +125°C without recalibration hardware. |
| Medical Device Usage Logs | Smart Meter Firmware Parameters |
|
Use Scenario: Logging sterilization cycles, usage counts, and maintenance timestamps in portable diagnostic equipment. IC Role / Device Role / Timing Role: Wear-leveling–agnostic event counter and timestamp buffer; written in small bursts using page-write mode. Use Value: Supports FDA audit trail requirements with 1M-cycle endurance and >200-year data retention at room temperature. |
Use Scenario: Storing tariff schedules, communication keys, and metering constants in ANSI C12.22-compliant electricity meters. IC Role / Device Role / Timing Role: Secure parameter store with hardware write-protection (BP1/BP0 + WP pin) preventing unauthorized firmware tampering. Use Value: Meets ANSI C12.22 security annex requirements for cryptographic key isolation and immutable billing parameters. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 25AA128T-I/ST | Wider VCC range (1.8–5.5 V); supports 3 MHz operation down to 1.8 V; identical pinout and instruction set | Better suited for battery-powered or ultra-low-voltage systems where 2.5 V minimum cannot be guaranteed | Select 25AA128T-I/ST only if system VCC may dip below 2.5 V; otherwise 25LC128T-I/ST offers tighter VCC tolerance and lower cost |
| AT25128B-SSHL-T | Same density and SPI interface; 5 ms max write time; but lacks HOLD pin and uses different STATUS register layout | Requires firmware adaptation for HOLD suspension and STATUS bit interpretation; no hardware pause capability | Choose AT25128B-SSHL-T only if HOLD functionality is unused and legacy Atmel toolchain support is required |
Compared with 25AA128T-I/ST and AT25128B-SSHL-T, the 25LC128T-I/ST delivers optimal balance of industrial temperature support, hardware write protection granularity, and HOLD-enabled interrupt resilience - making it preferred for deterministic real-time embedded systems.
Availability
25LC128T-I/ST is available at Aetrix Electronics and suitable for industrial PLCs, automotive sensor modules, medical diagnostics, and smart metering applications requiring stable component supply, long-lifecycle assurance, and AEC-Q100-qualified traceability.
Supply support for 25LC128T-I/ST includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a U.S.-based semiconductor company specializing in microcontrollers, analog devices, and memory solutions, with global manufacturing and quality certifications including ISO 9001 and IATF 16949.
The 25LC128T-I/ST belongs to Microchip's 25XX128 family of SPI EEPROMs, designed specifically for reliable, low-power nonvolatile storage in space-constrained embedded systems operating across extended industrial and automotive temperature ranges.
FAQ
What is the maximum clock frequency supported by the 25LC128T-I/ST?
The 25LC128T-I/ST supports up to 10 MHz clock frequency when VCC is between 4.5 V and 5.5 V. At 2.5 V ≤ VCC < 4.5 V, the maximum clock drops to 5 MHz. This voltage-dependent limit ensures reliable setup/hold timing for SI/SO signals and prevents metastability in internal latches during high-speed SPI transfers.
Does the 25LC128T-I/ST include hardware write protection?
Yes, the 25LC128T-I/ST includes dual-layer hardware write protection: a dedicated WP pin and nonvolatile BP0/BP1 bits in the STATUS register. When WP is low and WPEN=1, writes to the STATUS register are blocked. BP0/BP1 allow selective protection of 0%, 25%, 50%, or 100% of the memory array - providing flexible security for critical configuration data.
How does the HOLD function operate on the 25LC128T-I/ST?
The HOLD pin on the 25LC128T-I/ST suspends ongoing SPI communication without resetting the internal address pointer. To activate HOLD, the pin must be pulled low while SCK is low; SO, SI, and SCK enter high-impedance states. Resuming requires bringing HOLD high while SCK remains low. This allows MCUs to service higher-priority interrupts mid-transfer.
What package type is used for the 25LC128T-I/ST?
The 25LC128T-I/ST uses an 8-lead TSSOP (Thin Shrink Small Outline Package) with 0.65 mm lead pitch, JEDEC MO-153 compliant. It features gull-wing leads, a body size of 4.4 mm × 3.0 mm × 1.2 mm, and marking "25LC128I/ST" on the top surface - optimized for automated SMT assembly and high-density PCB layouts.
Is the 25LC128T-I/ST qualified for automotive applications?
Yes, the 25LC128T-I/ST is AEC-Q100 qualified (Grade 2) for automotive applications, rated for operation from –40°C to +105°C ambient temperature. It meets stress testing requirements for thermal cycling, humidity bias, and ESD (≥4 kV HBM), making it suitable for engine control units, ADAS sensors, and infotainment subsystems.
25LC128T-I/ST Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 128Kbit
- Memory Organization:
- 16K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 10 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
25LC128T-I/ST FAQ
1.How can I place an order for 25LC128T-I/ST through Aetrix?
Please submit a Request for Quotation (RFQ) for 25LC128T-I/ST on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 25LC128T-I/ST reliable?
The price and inventory of 25LC128T-I/ST are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 25LC128T-I/ST is usually 5 days.
3.What payment methods are accepted for 25LC128T-I/ST?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 25LC128T-I/ST transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 25LC128T-I/ST?
25LC128T-I/ST orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 25LC128T-I/ST order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 25LC128T-I/ST?
For technical support, including 25LC128T-I/ST datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 25LC128T-I/ST requirements.
6.How does Aetrix verify that 25LC128T-I/ST is sourced from the original manufacturer or authorized distributors?
All 25LC128T-I/ST products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 25LC128T-I/ST meets industry standards.
7.What is the process for return or replacement of 25LC128T-I/ST?
All 25LC128T-I/ST units undergo pre-shipment inspection (PSI). If there is an issue with 25LC128T-I/ST, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 25LC128T-I/ST part is unused and in its original packaging.
Return procedure for 25LC128T-I/ST:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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