Microchip Technology 25LC320AX-I/ST
- Part No.:
- 25LC320AX-I/ST
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
25LC320AX-I/ST.pdf
- Description:
- IC EEPROM 32KBIT SPI 8TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:4,474
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
25LC320AX-I/ST from Microchip Technology Inc. is a 32-Kbit SPI Serial EEPROM with 4096 × 8-bit organization, 32-byte page size, and industrial temperature range (−40°C to +85°C). It operates at up to 10 MHz clock frequency with 5 mA read/write current at 5.5 V and features hardware write protection via WP pin and STATUS register control. It is used in microcontroller-based systems for nonvolatile parameter storage, calibration data retention, and firmware configuration.
For engineers reviewing the 25LC320AX-I/ST datasheet, 25LC320AX-I/ST pinout, 25LC320AX-I/ST application, or 25LC320AX-I/ST equivalent, key selection criteria include SPI interface timing compliance (TCSS, TSU, THOLD), VCC range (2.5–5.5 V), block write protection granularity (0%, 25%, 50%, or 100% array), and AEC-Q100 qualification for automotive-grade reliability.
Technical Context
The 25LC320AX-I/ST implements a standard SPI Mode 0,0 or Mode 1,1 interface with separate SI (data-in) and SO (data-out) lines, CS-controlled device selection, and HOLD pin for transaction suspension without reset. Its internal architecture includes an 8-bit instruction register, page latches, and high-voltage generator for EEPROM programming.
It supports byte and page write operations (max 32 bytes/page), self-timed internal write cycles (≤5 ms), and sequential read with automatic address incrementing. Write enable requires explicit WREN instruction, and write protection is enforced via both volatile WEL bit and nonvolatile BP0/BP1 bits in the STATUS register, configurable via WRSR.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 32 Kbit (4096 × 8-bit), sufficient for storing boot configuration, sensor calibration tables, or device identity data in resource-constrained embedded systems. |
| Interface | SPI-compatible serial bus (Mode 0,0 / Mode 1,1), enabling direct connection to MCU SPI peripherals without level-shifting or protocol translation. |
| Max Clock Frequency | 10 MHz at VCC ≥ 4.5 V; scales down to 5 MHz (2.5–4.5 V) and 3 MHz (1.8–2.5 V), ensuring timing margin across supply variations. |
| Write Cycle Time | ≤5 ms internal self-timed erase/write, eliminating need for external polling delay management in host firmware. |
| Endurance & Retention | >1 million erase/write cycles and >200 years data retention at +25°C, supporting long-life industrial logging and infrequent update applications. |
| VCC Range | 2.5 V to 5.5 V, compatible with 3.3 V and 5 V logic domains and tolerant of brown-out conditions during power sequencing. |
| Temperature Range | Industrial grade: −40°C to +85°C, validated for operation in automotive cabin modules, industrial PLC I/O cards, and outdoor metering equipment. |
Pinout & Package
25LC320AX-I/ST is supplied in an 8-lead TSSOP package (3.0 mm × 4.4 mm body, 0.65 mm pitch), RoHS-compliant and marked "25LC320A" with "I" temperature grade and "ST" package code.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select Input | Active-low enable signal; deselecting forces SO into high-impedance state, allowing multi-device SPI bus sharing. |
| SO | Serial Data Output | Tri-state output delivering read data on falling SCK edge; transitions to high-Z immediately upon HOLD low assertion. |
| WP | Write-Protect Pin | Hardware lock for STATUS register nonvolatile bits when WPEN = 1; does not affect array writes unless BP0/BP1 are set. |
| VSS | Ground Reference | Primary return path for all digital and internal charge-pump currents; must be low-impedance for stable write-cycle timing. |
| SI | Serial Data Input | Latches instructions, addresses, and write data on rising SCK edge; ignored during HOLD mode regardless of SCK state. |
| SCK | Serial Clock Input | Synchronizes all SPI transactions; rising edge clocks SI data in, falling edge clocks SO data out per SPI specification. |
| HOLD | Transaction Pause Control | Halts ongoing SPI sequence without resetting internal state; requires SCK low before assertion and release to resume correctly. |
| VCC | Supply Voltage | Power source for logic and EEPROM programming; internal charge pump derives high voltage for cell programming from VCC. |
Key Features
| Feature | Design Value |
|---|---|
| Block Write Protection | Configurable via STATUS register to protect 0%, 25%, 50%, or 100% of memory array-enables secure partitioning of user data vs. factory calibration sectors. |
| Power-On Write Protection | Automatic reset of write enable latch and default STATUS register state prevents accidental writes during power-up transients or brownouts. |
| HOLD Functionality | Enables host MCU to service higher-priority interrupts mid-transaction without losing SPI context or requiring reinitialization. |
| ESD Robustness | >4 kV HBM rating ensures reliable operation in handling-sensitive manufacturing and field-repair environments without additional protection circuitry. |
| AEC-Q100 Qualification | Validated for automotive applications including body control modules and infotainment subsystems requiring extended temperature and lifetime reliability. |
Applications
| Automotive Body Control Module | Industrial Sensor Node |
|---|---|
Use Scenario: Storing seat position presets, mirror angle configurations, and lighting profiles in vehicle door modules. IC Role / Device Role / Timing Role: Nonvolatile configuration storage accessed via SPI during MCU boot and runtime updates; write operations occur only on user command or system event. Use Value: Enables personalized settings persistence across ignition cycles with guaranteed >200-year data retention and AEC-Q100-qualified reliability. | Use Scenario: Logging temperature, humidity, and pressure calibration coefficients in wireless environmental sensors deployed outdoors. IC Role / Device Role / Timing Role: Calibration data repository written once during factory trim and read repeatedly during sensor measurement cycles; uses sequential read for fast coefficient fetch. Use Value: Eliminates need for external trimming components and supports field recalibration via protected write access using WP pin and STATUS register controls. |
| Medical Infusion Pump | Smart Energy Meter |
Use Scenario: Recording drug delivery history, dosage limits, and maintenance alerts in battery-powered infusion devices. IC Role / Device Role / Timing Role: Secure audit log storage with write-protection enabled for critical safety parameters; HOLD pin used to pause writes during battery voltage sag events. Use Value: Ensures regulatory-compliant data integrity with >1M endurance cycles and hardware-enforced write-locking of immutable operational parameters. | Use Scenario: Storing tariff schedules, metering constants, and tamper-event timestamps in ANSI C12.22-compliant utility meters. IC Role / Device Role / Timing Role: Firmware-configurable parameter store accessed over isolated SPI; block protection isolates utility-defined constants from end-user writable fields. Use Value: Supports field-upgradable billing logic while preventing unauthorized modification of revenue-critical registers via BP0/BP1 status bit configuration. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 25AA320AT-I/ST | Wider VCC range (1.8–5.5 V); identical pinout, timing, and memory organization. | Better suited for mixed-voltage systems with 1.8 V logic domains; not AEC-Q100 qualified. | Select when operating below 2.5 V or when automotive qualification is unnecessary. |
| AT25DF321A-SH-B | 32 Mbit density, quad SPI interface, 8-pin SOIC package; no HOLD or WP pins; different instruction set. | Targeted at firmware code storage rather than parameter/configuration use; lacks hardware write protection granularity. | Choose only if migrating to larger memory capacity and accepting loss of HOLD/WP functionality and SPI compatibility. |
Compared with 25AA320AT-I/ST, the 25LC320AX-I/ST offers automotive qualification and tighter VCC minimum but excludes 1.8 V operation; versus AT25DF321A-SH-B, it provides deterministic SPI timing, hardware write protection, and direct drop-in replacement capability in legacy 32 Kbit designs.
Availability
25LC320AX-I/ST is available at Aetrix Electronics and suitable for automotive body control modules, industrial sensor nodes, medical infusion pumps, and smart energy meters requiring stable component supply, long-term lifecycle support, and AEC-Q100-compliant reliability.
Supply support for 25LC320AX-I/ST includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog devices, and memory solutions, headquartered in Chandler, Arizona, with global design and manufacturing operations.
The 25LC320A product line delivers cost-effective, SPI-compatible serial EEPROMs optimized for industrial and automotive applications demanding robust data retention, flexible write protection, and seamless integration with PIC® and other SPI-capable MCUs.
FAQ
What is the maximum clock frequency supported by the 25LC320AX-I/ST?
The 25LC320AX-I/ST supports up to 10 MHz clock frequency when VCC is between 4.5 V and 5.5 V. At lower supply voltages (2.5–4.5 V), the maximum clock drops to 5 MHz, and at 1.8–2.5 V, it is limited to 3 MHz. These derating values are specified in Table 1-2 of the DS20001828H datasheet and ensure reliable setup/hold timing margins across operating conditions. The 25LC320AX-I/ST must be operated within these limits to guarantee correct SPI communication and internal write-cycle completion.
Does the 25LC320AX-I/ST require external pull-up resistors on its SPI lines?
The 25LC320AX-I/ST does not require external pull-ups on SO, SI, or SCK - these pins are actively driven. However, CS and WP are active-low inputs with internal weak pull-ups disabled by default; external pull-ups (typically 4.7 kΩ to VCC) are recommended for CS to prevent spurious selection during power-up and for WP to ensure predictable write-protection state when not actively driven. HOLD also benefits from a pull-up to avoid unintended hold activation. These recommendations are consistent with Microchip's layout guidelines in AN1179 and DS20001828H Section 4.0.
How does the HOLD function behave during an active write cycle in the 25LC320AX-I/ST?
The HOLD function is disabled during an internal write cycle in the 25LC320AX-I/ST: pulling HOLD low after CS has gone high to initiate writing has no effect on the ongoing self-timed 5 ms erase/write operation. The device ignores HOLD transitions until the write completes and returns to standby. This behavior is explicitly documented in Section 2.6 and Figure 1-1 of DS20001828H. Therefore, the 25LC320AX-I/ST must rely on software polling of the WIP bit (via RDSR) or timeout-based waiting - not HOLD - to manage write completion.
Can the 25LC320AX-I/ST be used in a 1.8 V system?
No, the 25LC320AX-I/ST is not rated for 1.8 V operation. Its specified VCC range is 2.5 V to 5.5 V, as confirmed in the Device Selection Table and Table 1-1 of DS20001828H. Attempting to operate the 25LC320AX-I/ST below 2.5 V may result in unreliable read/write behavior, failed status register reads, or incomplete write cycles. For 1.8 V systems, the pin-compatible 25AA320A family (e.g., 25AA320AT-I/ST) is the appropriate alternative, offering identical functionality with 1.8 V minimum supply.
What package type does the 25LC320AX-I/ST use, and is it RoHS-compliant?
The 25LC320AX-I/ST uses an 8-lead TSSOP package (3.0 mm × 4.4 mm body, 0.65 mm pitch), identified by the "ST" suffix in the part number and confirmed in the Package Types section of DS20001828H. It is RoHS-compliant, as stated in the Features list on page 1 and verified by Microchip's packaging documentation. The package marking includes "25LC320A", temperature grade "I", and traceability codes - all consistent with Microchip's standard industrial-grade TSSOP labeling convention.
25LC320AX-I/ST Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 32Kbit
- Memory Organization:
- 4K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 10 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
25LC320AX-I/ST FAQ
1.How can I place an order for 25LC320AX-I/ST through Aetrix?
Please submit a Request for Quotation (RFQ) for 25LC320AX-I/ST on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 25LC320AX-I/ST reliable?
The price and inventory of 25LC320AX-I/ST are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 25LC320AX-I/ST is usually 5 days.
3.What payment methods are accepted for 25LC320AX-I/ST?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 25LC320AX-I/ST transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 25LC320AX-I/ST?
25LC320AX-I/ST orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 25LC320AX-I/ST order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 25LC320AX-I/ST?
For technical support, including 25LC320AX-I/ST datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 25LC320AX-I/ST requirements.
6.How does Aetrix verify that 25LC320AX-I/ST is sourced from the original manufacturer or authorized distributors?
All 25LC320AX-I/ST products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 25LC320AX-I/ST meets industry standards.
7.What is the process for return or replacement of 25LC320AX-I/ST?
All 25LC320AX-I/ST units undergo pre-shipment inspection (PSI). If there is an issue with 25LC320AX-I/ST, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 25LC320AX-I/ST part is unused and in its original packaging.
Return procedure for 25LC320AX-I/ST:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
25LC320AX-I/ST Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
