Microchip Technology 25LC320X-I/ST
- Part No.:
- 25LC320X-I/ST
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
25LC320X-I/ST.pdf
- Description:
- IC EEPROM 32KBIT SPI 2MHZ 8TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:4,643
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
25LC320X-I/ST from Microchip Technology Inc. is a 32 Kbit (4096 × 8) SPI serial EEPROM with industrial temperature range (−40°C to +85°C), 2 MHz max clock frequency at VCC = 2.5–5.5 V, and 8-pin TSSOP package. It features hardware write protection via WP pin, HOLD functionality for interrupt-safe pausing, and 32-byte page write capability. It is used in embedded systems for storing calibration data, configuration parameters, and firmware patches.
For engineers reviewing the 25LC320X-I/ST datasheet, 25LC320X-I/ST pinout, 25LC320X-I/ST application, or 25LC320X-I/ST equivalent, key selection criteria include VCC compatibility (2.5–5.5 V), SPI timing compliance (tCSH, tHOLD), endurance (1M E/W cycles), data retention (>200 years), and block protection granularity (1/4, 1/2, or full array).
Technical Context
The 25LC320X-I/ST implements a standard SPI Mode 0,0 interface with separate SI (data in) and SO (data out) lines, requiring CS, SCK, WP, and HOLD control signals. Its internal architecture includes an 8-bit instruction register, STATUS register with WIP/WEL/BP0/BP1 bits, and high-voltage generator for EEPROM programming.
Write operations require explicit WREN instruction followed by WRITE command and address/data; page writes are limited to 32 bytes within the same 32-byte-aligned boundary. The HOLD pin suspends ongoing SPI transfers without resetting the sequence, enabling host MCU to service higher-priority interrupts while preserving transaction state.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 32 Kbit (4096 × 8 bits); supports up to 4096 unique byte-addressable locations |
| Interface | SPI-compatible serial bus (Mode 0,0); requires CS, SCK, SI, SO, WP, HOLD, VCC, VSS |
| Max clock frequency | 2 MHz at VCC = 2.5–5.5 V; defines maximum sustained data throughput (~2 Mbps) |
| Write cycle time | 5 ms maximum internal write time per page or byte; determines minimum delay before status polling or next operation |
| Endurance & retention | 1 million erase/write cycles; >200 years data retention at 85°C - validated for long-life industrial logging |
| Supply current | 500 μA typical read current (VCC = 2.5 V, fCLK = 2 MHz); 3 mA max write current; 500 nA standby - enables low-power battery operation |
| Temperature range | Industrial grade: −40°C to +85°C - qualified for use in programmable logic controllers and sensor nodes |
Pinout & Package
25LC320X-I/ST uses an 8-pin Plastic TSSOP (4.4 mm body width) package with ST suffix, pin-compatible with SOIC-8 but thinner and footprint-optimized. Pin 1 is CS; pin 8 is VCC; no NC pins in this variant.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1 (CS) | Chip Select Input | Active-low enable; deselecting forces SO into high-impedance to share SPI bus with other devices |
| 2 (SO) | Serial Data Output | Tri-state output; data shifted out on falling edge of SCK; high-Z when CS high or HOLD active |
| 3 (WP) | Write-Protect Input | Hardware lock for STATUS register nonvolatile bits when WPEN = 1; grounded to prevent accidental writes |
| 4 (VSS) | Ground | Reference return path for all digital and internal HV circuits; must be low-impedance |
| 5 (SI) | Serial Data Input | Latches instruction/address/data on rising edge of SCK; accepts MSB-first 8-bit commands |
| 6 (SCK) | Serial Clock Input | Synchronizes all SPI transfers; timing-critical for tCSH, tTCSS, tTHD compliance |
| 7 (HOLD) | Hold Input | Pauses ongoing SPI transfer (e.g., during MCU interrupt); requires SCK low to assert/deassert |
| 8 (VCC) | Supply Voltage | 2.5–5.5 V operating range; powers logic, charge pump, and I/O buffers; bypass capacitor required |
Key Features
| Feature | Design Value |
|---|---|
| Block write protection | Selectable 0%, 25%, 50%, or 100% array protection via BP0/BP1 bits - prevents corruption of critical firmware sections |
| HOLD function | Interrupt-safe SPI pause/resume without retransmission - eliminates race conditions during real-time task switching |
| Power-on write disable | WEL latch resets at power-up; prevents spurious writes during brown-out or reset sequences |
| Page write buffer | 32-byte page write capability - reduces SPI overhead vs. byte-by-byte writes; improves firmware update efficiency |
| ESD robustness | >4000 V HBM ESD rating - ensures reliability in handling-sensitive industrial assembly environments |
Applications
| Industrial Sensor Calibration | Medical Device Configuration |
|---|---|
|
Use Scenario: Storing factory-calibrated sensor offset/gain coefficients and linearization tables in portable gas analyzers. IC Role / Device Role / Timing Role: Nonvolatile parameter storage accessed during boot and periodic self-test; SPI reads occur at <200 kHz during initialization. Use Value: Enables field-replaceable sensors without recalibration; 1M endurance supports lifetime recalibration cycles across device service life. |
Use Scenario: Holding user-configurable therapy parameters (e.g., infusion rate limits, alarm thresholds) in battery-powered insulin pumps. IC Role / Device Role / Timing Role: Secure, low-power configuration store; write operations occur only during setup mode with WP asserted. Use Value: 500 nA standby current extends battery life; hardware WP prevents runtime corruption during ESD events or software faults. |
| PLC Firmware Patch Storage | Automotive Body Control Module Settings |
|
Use Scenario: Hosting hot-fix patches for ladder logic execution engines in DIN-rail mounted PLCs. IC Role / Device Role / Timing Role: Field-upgradable code repository; accessed via isolated SPI bus during maintenance windows. Use Value: 2 MHz SPI speed enables sub-second patch loading; 32-byte page writes minimize bus occupancy during critical control cycles. |
Use Scenario: Retaining seat/mirror position memory and lighting profiles across ignition cycles in entry-level BCMs. IC Role / Device Role / Timing Role: Persistent settings store; writes triggered by user input with HOLD used to defer updates until idle bus periods. Use Value: −40°C to +85°C rating ensures operation in under-hood environments; 200-year retention avoids memory degradation over vehicle lifetime. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 25AA320-I/ST | 1.8–5.5 V supply range; 1 MHz max clock; identical pinout and instruction set | Better suited for mixed-voltage systems with 1.8 V MCUs; lower speed acceptable for infrequent config storage | Choose when system VCC may dip below 2.5 V or when 1 MHz SPI suffices |
| 25LC320T-I/ST | Identical electrical specs and pinout; supplied in tape-and-reel (T suffix) instead of tube | Same functional behavior; optimized for automated SMT assembly rather than manual prototyping | Choose for volume production with pick-and-place; no design or layout impact |
Compared with 25LC320X-I/ST, the 25AA320-I/ST offers wider VCC flexibility at reduced speed, while the 25LC320T-I/ST differs only in packaging format - both retain identical timing, endurance, and protection features for drop-in replacement in compatible layouts.
Availability
25LC320X-I/ST is available at Aetrix Electronics and suitable for industrial automation, medical instrumentation, and automotive body electronics requiring stable component supply, long-term obsolescence management, and traceable sourcing.
Supply support for 25LC320X-I/ST includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontroller, analog, and memory solutions, headquartered in Chandler, Arizona, with global design and manufacturing operations.
The 25LC320X-I/ST belongs to Microchip's SPI serial EEPROM product line, designed specifically for reliable, low-power nonvolatile storage in space-constrained industrial and automotive applications where write-protection integrity and long-term data retention are critical.
FAQ
What is the supply voltage range supported by the 25LC320X-I/ST?
The 25LC320X-I/ST operates from 2.5 V to 5.5 V DC. This range is specified for industrial temperature operation (−40°C to +85°C) and enables direct interfacing with 3.3 V and 5 V microcontrollers without level shifting. Operation below 2.5 V is not guaranteed and may result in unreliable write cycles or STATUS register reads.
Does the 25LC320X-I/ST support page writes, and what is the maximum page size?
Yes, the 25LC320X-I/ST supports page writes with a maximum size of 32 bytes. Page boundaries are aligned to 32-byte intervals (e.g., 0x0000–0x001F). Attempting to cross a page boundary during a single write sequence causes the internal address counter to roll over, overwriting data at the start of the page - proper address management is required in firmware.
How does the HOLD pin function during an active SPI transaction on the 25LC320X-I/ST?
The HOLD pin on the 25LC320X-I/ST pauses an ongoing SPI transaction when pulled low while SCK is low. During HOLD, SI, SCK, and SO enter high-impedance states and ignore input transitions except CS. Resuming requires bringing HOLD high while SCK remains low; the transaction continues from the exact bit position where it was paused.
What write protection mechanisms are implemented in the 25LC320X-I/ST?
The 25LC320X-I/ST implements dual-layer write protection: (1) software-controlled block protection (BP0/BP1 bits) enabling 0%, 25%, 50%, or 100% array lockdown, and (2) hardware write protection via the WP pin when WPEN = 1 in the STATUS register. Both mechanisms independently guard against unintended writes to memory or STATUS bits.
Is the 25LC320X-I/ST pin-compatible with other variants in the 25XX320 family?
Yes, the 25LC320X-I/ST shares identical 8-pin TSSOP (ST) pinout with 25AA320X-I/ST and 25C320X-I/ST. All three variants use the same CS/SO/WP/VSS/SI/SCK/HOLD/VCC assignment. However, voltage ranges and max clock frequencies differ - substituting requires verifying VCC and timing compliance in the target application.
25LC320X-I/ST Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 32Kbit
- Memory Organization:
- 4K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 2 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
25LC320X-I/ST FAQ
1.How can I place an order for 25LC320X-I/ST through Aetrix?
Please submit a Request for Quotation (RFQ) for 25LC320X-I/ST on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 25LC320X-I/ST reliable?
The price and inventory of 25LC320X-I/ST are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 25LC320X-I/ST is usually 5 days.
3.What payment methods are accepted for 25LC320X-I/ST?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 25LC320X-I/ST transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 25LC320X-I/ST?
25LC320X-I/ST orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 25LC320X-I/ST order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 25LC320X-I/ST?
For technical support, including 25LC320X-I/ST datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 25LC320X-I/ST requirements.
6.How does Aetrix verify that 25LC320X-I/ST is sourced from the original manufacturer or authorized distributors?
All 25LC320X-I/ST products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 25LC320X-I/ST meets industry standards.
7.What is the process for return or replacement of 25LC320X-I/ST?
All 25LC320X-I/ST units undergo pre-shipment inspection (PSI). If there is an issue with 25LC320X-I/ST, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 25LC320X-I/ST part is unused and in its original packaging.
Return procedure for 25LC320X-I/ST:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
25LC320X-I/ST Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
