onsemi 2N5462G
- Part No.:
- 2N5462G
- Manufacturer:
- onsemi
- Category:
- JFETs
- Package:
- TO-226-3, TO-92-3 Long Body
- Datasheet:
-
2N5462G.pdf
- Description:
- JFET P-CH 40V TO92
- Quantity:
- Payment:

- Shipping:

Inventory:7,802
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Product details
Overview
2N5462G from onsemi is a P-channel depletion-mode JFET amplifier optimized for low-noise, high-input-impedance analog signal conditioning in audio preamplifiers and sensor front-ends. It delivers IDSS = −4.0 to −16 mA, VGS(off) = 1.8 to 9.0 V, |yfs| = 2000–6000 mhos, Ciss = 5.0–7.0 pF, and en = 60–115 nV/√Hz at 100 Hz, operating across −65°C to +135°C junction temperature.
For engineers reviewing the 2N5462G datasheet, pinout, applications, or equivalent options, key selection criteria include gate-source cutoff voltage range, zero-gate drain current tolerance, forward transfer admittance at 1 kHz, noise performance at low frequencies, and TO-92 thermal derating behavior under continuous DC bias.
Technical Context
This JFET operates as a voltage-controlled current source with depletion-mode P-channel architecture, requiring negative VGS for conduction control. Its transconductance (|yfs|) and output resistance (ross) are specified at VDS = 15 Vdc and f = 1.0 kHz, supporting stable small-signal amplification in common-source configurations.
Designed for DC-coupled and AC-coupled linear amplification, it exhibits low gate leakage (IGSS ≤ 5.0 nAdc at 20 V), tight capacitance matching (Ciss/Crss ratio ~5:1), and predictable VGS(off) distribution across production lots-enabling consistent bias point setting in discrete gain stages.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| IDSS | −4.0 to −16 mA: Sets maximum drain current at VGS = 0; defines usable bias range for linear operation. |
| VGS(off) | 1.8 to 9.0 V: Gate-source voltage required to pinch off channel; determines minimum negative bias needed for cutoff. |
| |yfs| | 2000–6000 mhos: Small-signal transconductance at 1 kHz; directly impacts voltage gain in common-source stage. |
| en | 60–115 nV/√Hz @ 100 Hz: Equivalent input noise voltage; critical for microphone preamps and precision sensor interfaces. |
| Ciss | 5.0–7.0 pF: Input capacitance at VDS = 15 V, VGS = 0, 1 MHz; limits high-frequency bandwidth in high-Z source applications. |
| PD @ 25°C | 350 mW: Maximum power dissipation; requires 2.8 mW/°C derating above ambient, constraining continuous DC load design. |
Pinout & Package
2N5462G is housed in a Pb-free TO-92 package (Case 29, Style 7), with standardized lead configuration and mechanical dimensions per ON Semiconductor's CASE 29-11 specification.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Source | Reference node for gate-source voltage; connected to signal ground or bias network in common-source topology. |
| 2 | Drain | Output current terminal; connects to load resistor or active load; polarity inverted relative to N-channel JFETs. |
| 3 | Gate | Control electrode; high-impedance input (IGSS ≤ 5 nA); requires negative bias relative to source for operation. |
Key Features
| Feature | Design Value |
|---|---|
| P-channel depletion mode | Enables self-biasing without external gate supply; simplifies single-rail analog front-end design. |
| Low input capacitance (Ciss ≤ 7.0 pF) | Maintains high-frequency response when driving from high-impedance sources like piezoelectric sensors. |
| Low 1/f noise (en ≤ 115 nV/√Hz) | Supports high-fidelity audio amplification and low-drift instrumentation amplifier input stages. |
| Wide operating temperature (−65°C to +135°C) | Validated for industrial and automotive under-hood signal conditioning where thermal stability is critical. |
Applications
| Microphone Preamp | Thermocouple Amplifier |
|---|---|
Use Scenario: Low-noise amplification of millivolt-level signals from electret condenser microphones in portable audio devices. IC Role / Device Role / Timing Role: Discrete JFET input stage providing high input impedance (>10⁹ Ω) and minimal added noise before op-amp buffering. Use Value: Achieves <65 dB(A) equivalent input noise floor with 10 kΩ source impedance, meeting IEC 61672 Class 2 requirements. | Use Scenario: Signal conditioning of thermocouple outputs in industrial temperature monitoring systems with wide ambient range. IC Role / Device Role / Timing Role: First-stage amplifier with cold-junction compensation interface and DC-coupled offset control. Use Value: Enables sub-0.5°C measurement accuracy over −40°C to +125°C ambient by minimizing thermal EMF and bias current drift. |
| Photodiode Transimpedance Stage | Oscillator Frequency Control Element |
Use Scenario: High-gain, low-noise current-to-voltage conversion for silicon photodiodes in optical smoke detectors. IC Role / Device Role / Timing Role: JFET-based transimpedance amplifier input device with ultra-low gate leakage (<5 nA). Use Value: Supports >10⁹ Ω feedback resistors without significant leakage-induced offset drift or bandwidth reduction. | Use Scenario: Variable-frequency oscillator core in tunable RF receiver local oscillators for ISM-band wireless modules. IC Role / Device Role / Timing Role: Voltage-variable reactance element in Clapp or Colpitts topology, leveraging gate-source capacitance modulation. Use Value: Provides >10:1 tuning ratio with <1% frequency drift over temperature due to matched Ciss/VGS characteristics. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar JFET amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| J310 | N-channel depletion mode; IDSS = −24 to −60 mA; VGS(off) = −0.5 to −1.5 V; higher |yfs| but higher noise (en ≈ 150 nV/√Hz). | Requires positive VDD referenced to source; unsuitable for direct replacement in P-channel bias networks. | Select only when redesigning for N-channel topology and higher transconductance is prioritized over noise floor. |
| 2SK117 | P-channel; IDSS = −1.5 to −4.5 mA; VGS(off) = −0.5 to −2.5 V; lower |yfs| (1500–3500 mhos); Ciss = 3.5 pF. | Narrower VGS(off) range reduces bias flexibility; lower IDSS limits drive capability in high-gain stages. | Prefer for ultra-low-capacitance applications where 3.5 pF Ciss enables >20 MHz bandwidth, accepting reduced gain margin. |
Compared with J310 and 2SK117, the 2N5462G offers the widest VGS(off) range (1.8–9.0 V) and lowest 100-Hz noise (60–115 nV/√Hz), making it uniquely suited for precision DC-coupled amplifiers where gate bias stability and low-frequency SNR are critical.
Availability
2N5462G is available at Aetrix Electronics and suitable for audio preamplifiers, thermocouple signal conditioners, and photodiode transimpedance amplifiers requiring stable component supply, long-term obsolescence management, and Pb-free compliance.
Supply support for 2N5462G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power, analog, sensing, and connectivity solutions for automotive, industrial, cloud, and consumer markets.
The 2N5462G belongs to onsemi's legacy JFET amplifier family designed specifically for high-fidelity analog signal acquisition, emphasizing low noise, stable DC parameters, and robust thermal performance in discrete front-end stages.
FAQ
What is the maximum drain-source voltage rating for the 2N5462G?
The 2N5462G has no explicit VDS(max) rating in its datasheet. Instead, it specifies VDG (drain-to-gate voltage) = 40 Vdc and VGSR (reverse gate-to-source voltage) = 40 Vdc. Safe operation requires VDS ≤ VDG − |VGS|, limiting practical VDS to ≤35 V under typical bias conditions. Absolute maximum stress ratings do not imply functional operation at those levels.
Does the 2N5462G have a guaranteed minimum transconductance value?
Yes-the 2N5462G guarantees |yfs| ≥ 2000 mhos at VDS = 15 Vdc, VGS = 0, and f = 1.0 kHz. This minimum ensures predictable small-signal gain in common-source amplifier designs, though actual values typically reach 5000–6000 mhos depending on IDSS lot distribution.
Can the 2N5462G be used in surface-mount designs?
No-the 2N5462G is exclusively offered in through-hole TO-92 packaging (Case 29). onsemi does not manufacture or qualify a surface-mount variant. Designers requiring SMT compatibility must select alternative JFETs such as the SOT-23 packaged MMBFJ175 or PMBFJ175, which differ in parameter spread and thermal performance.
How does gate leakage current affect bias stability in the 2N5462G?
With IGSS ≤ 5.0 nAdc at VGS = 20 Vdc and TA = 25°C, gate leakage introduces negligible error in high-impedance bias networks (e.g., 10 MΩ source resistors). However, at 100°C, IGSS rises to ≤1.0 μAdc-potentially causing >10 mV shift in VGS in poorly decoupled circuits, necessitating thermal-aware layout and bypassing.
Is the 2N5462G suitable for RF amplifier applications above 10 MHz?
The 2N5462G is characterized up to 1 MHz for capacitance and 30 MHz for y-parameters, but its |yfs| rolls off significantly above 5 MHz. While usable in narrowband HF oscillator tanks (e.g., 1–5 MHz Clapp), it is not recommended for broadband RF amplification above 10 MHz due to rising output conductance (|yos| ≤ 75 mhos) and uncharacterized S-parameter behavior.
2N5462G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- -
- Package/Case:
- TO-226-3, TO-92-3 Long Body
- Packaging:
- Bulk
- Product Status:
- Obsolete
- FET Type:
- P-Channel
- Voltage - Breakdown (V(BR)GSS):
- 40 V
- Drain to Source Voltage (Vdss):
- -
- Current - Drain (Idss) @ Vds (Vgs=0):
- 4 mA @ 15 V
- Current Drain (Id) - Max:
- -
- Voltage - Cutoff (VGS off) @ Id:
- 1.8 V @ 1 µA
- Input Capacitance (Ciss) (Max) @ Vds:
- 7pF @ 15V
- Resistance - RDS(On):
- -
- Power - Max:
- 350 mW
- Operating Temperature:
- -65°C ~ 135°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- TO-92 (TO-226)
2N5462G FAQ
1.How can I place an order for 2N5462G through Aetrix?
Please submit a Request for Quotation (RFQ) for 2N5462G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 2N5462G reliable?
The price and inventory of 2N5462G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 2N5462G is usually 5 days.
3.What payment methods are accepted for 2N5462G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 2N5462G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 2N5462G?
2N5462G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 2N5462G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 2N5462G?
For technical support, including 2N5462G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 2N5462G requirements.
6.How does Aetrix verify that 2N5462G is sourced from the original manufacturer or authorized distributors?
All 2N5462G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 2N5462G meets industry standards.
7.What is the process for return or replacement of 2N5462G?
All 2N5462G units undergo pre-shipment inspection (PSI). If there is an issue with 2N5462G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 2N5462G part is unused and in its original packaging.
Return procedure for 2N5462G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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