Microchip Technology 47L04T-I/ST
- Part No.:
- 47L04T-I/ST
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
47L04T-I/ST.pdf
- Description:
- IC EERAM 4KBIT I2C 1MHZ 8TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:1,472
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
47L04T-I/ST from Microchip Technology is a 4 Kbit I²C serial EERAM combining 512 × 8-bit SRAM with integrated EEPROM backup, operating from 2.7V–3.6V, supporting up to 1 MHz I²C, and featuring automatic power-loss store/recall via external VCAP capacitor. It delivers infinite SRAM write cycles, >1 million EEPROM store cycles, and >200-year data retention - deployed in automotive infotainment control modules for nonvolatile parameter storage during ignition cycling.
For engineers reviewing the 47L04T-I/ST datasheet, 47L04T-I/ST pinout, 47L04T-I/ST application, or 47L04T-I/ST equivalent, key selection criteria include VCC range (2.7–3.6 V), Auto-Store trip voltage (2.4–2.6 V), 8 ms max Store time, software/hardware store control, and AEC-Q100 qualification for extended temperature operation (-40°C to +125°C).
Technical Context
The 47L04T-I/ST implements a dual-memory architecture where SRAM serves as fast-access working memory and EEPROM provides high-endurance nonvolatile backup. Its I²C interface uses Schmitt-trigger inputs, supports cascading up to four devices, and enforces strict timing per SMBus v2.0 with 500 ns minimum clock high/low times.
Power management is handled through VCAP-based auto-store detection: when VCC falls below VTRIP (2.4–2.6 V), the device initiates automatic SRAM-to-EEPROM transfer. The STATUS register (address 00h) controls ASE (Auto-Store Enable), BP<2:0> (block protection), and AM (Array Modified) status, while the COMMAND register (55h) executes software Store (33h) and Recall (DDh) operations.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Density | 4 Kbit (512 × 8-bit SRAM + EEPROM backup) |
| VCC Range | 2.7 V to 3.6 V - compatible with 3.3 V systems; excludes 5 V logic domains |
| I²C Speed | Up to 1 MHz - enables high-throughput configuration updates without bus contention |
| Store Time | ≤8 ms - ensures full SRAM backup before brownout-induced system reset |
| Data Retention | >200 years - guarantees long-term calibration or fault-log persistence across product lifecycle |
| Endurance | 1,000,000 EEPROM store cycles - supports frequent parameter logging in telematics units |
| VTRIP | 2.4–2.6 V - precise low-voltage threshold triggers reliable auto-store at safe margin above POR |
| Temp Range | -40°C to +125°C (Extended) - validated for under-hood automotive environments |
Pinout & Package
47L04T-I/ST is housed in an 8-lead TSSOP (Thin Shrink Small Outline Package) with 0.65 mm lead pitch, JEDEC MO-153 compliant, suitable for automated SMT assembly and thermal performance in compact automotive PCBs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCAP | Auto-store energy reservoir | Connects external 5–6.8 µF capacitor to sustain internal charge pump during VCC collapse |
| A1, A2 | Device address select | Set hardware I²C client address bits (A2:A1); enable up to four devices on same bus |
| VSS | Ground reference | Return path for all internal logic and memory arrays; requires low-impedance connection |
| VCC | Supply voltage input | 2.7–3.6 V main power; powers SRAM, EEPROM controller, and I²C interface |
| HS | Hardware store trigger | Pulse ≥150 ns high to initiate immediate SRAM→EEPROM transfer independent of VCC state |
| SCL | I²C clock input | Drives synchronous serial communication; Schmitt-triggered for noise immunity |
| SDA | I²C bidirectional data | Open-drain I/O with ±1 µA leakage; supports multi-master arbitration and ACK/NACK signaling |
Key Features
| Feature | Design Value |
|---|---|
| Auto-store on power loss | Guaranteed SRAM→EEPROM transfer using external VCAP capacitor - eliminates need for backup battery or supercapacitor circuitry |
| Software write protection | Configurable block protection (1/64 to full array) via STATUS register BP<2:0> bits - prevents accidental overwrites of critical firmware parameters |
| Hardware store pin (HS) | Asynchronous, edge-triggered manual store initiation - enables deterministic backup on system-initiated events (e.g., button press, error condition) |
| AEC-Q100 qualified | Validated for automotive Extended temperature range (-40°C to +125°C) - meets reliability requirements for engine control and ADAS subsystems |
| Zero-cycle-delay reads/writes | Immediate data availability after ACK - reduces I²C transaction latency for real-time sensor calibration updates |
Applications
| Automotive Body Control Module | Industrial PLC Configuration Storage |
|---|---|
Use Scenario: Storing door lock settings, mirror position presets, and lighting profiles across vehicle power cycles. IC Role / Device Role / Timing Role: Nonvolatile SRAM buffer with automatic power-fail backup - retains user preferences without external NV memory or battery. Use Value: Eliminates backup battery maintenance; achieves >200-year data retention and 1M+ store cycles for lifetime vehicle operation. | Use Scenario: Preserving ladder logic configuration, I/O mapping, and alarm thresholds during factory floor power interruptions. IC Role / Device Role / Timing Role: High-reliability configuration memory with hardware-triggered store - ensures deterministic state recovery after brownouts. Use Value: Reduces PLC reboot time by recalling full configuration in ≤2 ms; supports industrial-grade endurance at -40°C to +125°C. |
| Medical Infusion Pump Calibration | Smart Energy Meter Firmware Parameters |
Use Scenario: Securing dose calibration constants, delivery history, and safety limits across clinical power-down events. IC Role / Device Role / Timing Role: Tamper-resistant, software-protected memory with verified recall integrity - critical for FDA Class II device data integrity. Use Value: BP<2:0> bits lock top 1/8 of array (1C0h–1FFh) to prevent runtime corruption; AM bit confirms modification status pre-recall. | Use Scenario: Storing tariff schedules, metering constants, and tamper-event logs in ANSI C12.22-compliant smart meters. IC Role / Device Role / Timing Role: AEC-Q100-qualified EERAM serving as secure, low-power configuration vault - operates reliably in outdoor utility enclosures. Use Value: 40 µA standby current extends battery life in backup-powered meters; 1 MHz I²C enables rapid firmware field updates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar nonvolatile SRAM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| FM24CL04B-G | 4 Kbit F-RAM (not EERAM); no VCAP required; 10¹⁴ read/write endurance; 2.7–3.6 V | No auto-store timing dependency; faster random writes; no recall delay | Choose for ultra-high-write-cycle applications where deterministic latency matters more than cost-per-bit |
| AT24C04D-SSHM-T | 4 Kbit I²C EEPROM only; no SRAM layer; 1.7–5.5 V; 1 MHz interface | Requires host-managed write buffering; slower write speed (5 ms/page); no instant-read capability | Choose when absolute lowest BOM cost is prioritized and write frequency is low (<100x/day) |
Compared with FM24CL04B-G and AT24C04D-SSHM-T, the 47L04T-I/ST uniquely combines instant SRAM access with EEPROM-level nonvolatility and autonomous power-loss response - making it optimal for systems requiring both speed and guaranteed state preservation without host intervention.
Availability
47L04T-I/ST is available at Aetrix Electronics and suitable for automotive body control, industrial PLC configuration, medical infusion pump calibration, and smart energy meter firmware storage requiring stable component supply across extended temperature and long-lifecycle programs.
Supply support for 47L04T-I/ST includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog, FPGA, and memory solutions, headquartered in Chandler, Arizona, with global design and manufacturing operations.
The 47L04T-I/ST belongs to Microchip's EERAM family - engineered specifically for applications needing SRAM-speed access with EEPROM-level nonvolatility and autonomous power-loss resilience in harsh environments.
FAQ
What is the function of the VCAP pin on the 47L04T-I/ST?
The VCAP pin on the 47L04T-I/ST connects to an external 5–6.8 µF capacitor that supplies energy during VCC collapse, enabling automatic SRAM-to-EEPROM store when VCC drops below 2.4–2.6 V. If VCAP is unconnected, the pin must be tied to VCC and Auto-Store disabled (ASE = 0) to prevent EEPROM corruption. This design eliminates reliance on backup batteries while ensuring deterministic nonvolatile backup in automotive and industrial systems using the 47L04T-I/ST.
How does the 47L04T-I/ST handle write protection?
The 47L04T-I/ST implements software-configurable write protection via three BP<2:0> bits in its STATUS register (00h), allowing selective locking of memory blocks - from none to the entire 512-byte array (e.g., BP<2:0> = 111 protects addresses 000h–1FFh). Protection is nonvolatile and persists across power cycles. Attempts to write to protected regions result in NACK after the data byte, halting the operation without incrementing the address pointer - a critical safeguard for firmware-critical data stored in the 47L04T-I/ST.
Can the 47L04T-I/ST operate at 1 MHz I²C speed across its full temperature range?
Yes, the 47L04T-I/ST supports 1 MHz I²C operation from -40°C to +125°C (Extended temperature grade), with guaranteed AC timing including 500 ns minimum SCL high/low times and 300 ns max rise/fall times. Its Schmitt-trigger inputs suppress noise on noisy automotive or industrial buses, and zero-cycle-delay reads/writes ensure deterministic throughput. This full-range 1 MHz capability is explicitly specified in DS20005371E and makes the 47L04T-I/ST suitable for high-speed configuration updates in real-time systems.
What happens if a Hardware Store (HS) pulse occurs during an active I²C transaction on the 47L04T-I/ST?
If an HS pulse occurs during an SRAM read or write operation on the 47L04T-I/ST, the ongoing I²C transaction is immediately aborted to prioritize the Store operation. The device stops acknowledging further bytes, releases SDA, and begins SRAM-to-EEPROM transfer within nanoseconds. After completion (≤8 ms), the 47L04T-I/ST resumes normal I²C responsiveness. This behavior is documented in Section 2.3.1 and ensures data integrity even during concurrent host access - a key reliability feature of the 47L04T-I/ST.
Is the 47L04T-I/ST pin-compatible with other devices in the 47XXX family?
Yes, the 47L04T-I/ST shares identical 8-lead TSSOP pinout, electrical characteristics, and register map with all members of the 47L04/47C04/47L16/47C16 family, including 47L04T-I/SN (SOIC) and 47L04-I/P (PDIP). Pin functions (VCAP, A1, A2, VSS, VCC, HS, SCL, SDA), timing, and command set are fully consistent. However, voltage range differs: 47L04 variants require 2.7–3.6 V, while 47C04 uses 4.5–5.5 V - so direct substitution requires matching VCC domain, but PCB layout remains unchanged for the 47L04T-I/ST.
47L04T-I/ST Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EERAM
- Technology:
- EEPROM, SRAM
- Memory Size:
- 4Kbit
- Memory Organization:
- 512 x 8
- Memory Interface:
- I2C
- Clock Frequency:
- 1 MHz
- Write Cycle Time - Word, Page:
- 1ms
- Access Time:
- 400 ns
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
47L04T-I/ST FAQ
1.How can I place an order for 47L04T-I/ST through Aetrix?
Please submit a Request for Quotation (RFQ) for 47L04T-I/ST on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 47L04T-I/ST reliable?
The price and inventory of 47L04T-I/ST are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 47L04T-I/ST is usually 5 days.
3.What payment methods are accepted for 47L04T-I/ST?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 47L04T-I/ST transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 47L04T-I/ST?
47L04T-I/ST orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 47L04T-I/ST order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 47L04T-I/ST?
For technical support, including 47L04T-I/ST datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 47L04T-I/ST requirements.
6.How does Aetrix verify that 47L04T-I/ST is sourced from the original manufacturer or authorized distributors?
All 47L04T-I/ST products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 47L04T-I/ST meets industry standards.
7.What is the process for return or replacement of 47L04T-I/ST?
All 47L04T-I/ST units undergo pre-shipment inspection (PSI). If there is an issue with 47L04T-I/ST, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 47L04T-I/ST part is unused and in its original packaging.
Return procedure for 47L04T-I/ST:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
47L04T-I/ST Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
