Skyworks Solutions Inc. 510CBA25M0000AAG
- Part No.:
- 510CBA25M0000AAG
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Oscillators
- Package:
- 4-SMD, No Lead
- Datasheet:
-
510CBA25M0000AAG.pdf
- Description:
- XTAL OSC XO 25.0000MHZ CMOS SMD
- Quantity:
- Payment:

- Shipping:

Inventory:115
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Product details
Overview
510CBA25M0000AAG from Skyworks Solutions is a factory-programmed, 25 MHz CMOS-output crystal oscillator (XO) in a 5 × 7 mm 4-pin surface-mount package, operating from 3.3 V with ±30 ppm total stability over –40 to +85 °C and 10-year aging. It delivers low-jitter timing for FPGA clocking, Gigabit Ethernet PHYs, and telecom line cards requiring stable, noise-immune reference clocks.
For engineers reviewing the 510CBA25M0000AAG datasheet, 510CBA25M0000AAG pinout, 510CBA25M0000AAG application, or 510CBA25M0000AAG equivalent, this part provides a drop-in, RoHS-compliant timing solution with guaranteed startup time ≤10 ms, OE-controlled output enable/disable, and production-tested crystal ESR/DLD for high-reliability deployment.
Technical Context
The 510CBA25M0000AAG implements Skyworks' DSPLL® synthesis architecture, using a fixed-frequency crystal resonator and on-chip digital PLL to generate its precise 25.000000 MHz output - eliminating frequency-specific crystals while maintaining superior stability and mechanical robustness. Its integrated LDO regulator filters supply noise, enabling sub-1 ps RMS phase jitter performance even under noisy rail conditions.
This Si510-series XO supports active-high output enable (OE on Pin 1), operates across full industrial temperature range, and features runt suppression on power-up and OE transitions. The device is configured at factory shipment - no field programming required - and complies with MIL-STD-883 environmental reliability standards.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Nominal Frequency | 25.000000 MHz - exact factory-programmed output; supports synchronous logic timing with zero frequency deviation tolerance in final design |
| Output Format | CMOS - single-ended, rail-to-rail swing with 8 mA drive strength at 3.3 V; compatible with standard logic inputs without level-shifting |
| Total Stability | ±30 ppm - includes initial accuracy, temperature variation (–40 to +85 °C), supply/load changes, shock/vibration, and 10-year aging at 40 °C |
| Supply Voltage | 3.3 V ±10% - internally regulated via on-chip LDO; rejects >3 ps RMS jitter increase from 100 mVPP supply noise at 10–1 MHz |
| Startup Time | ≤10 ms - time from minimum VDD to output within frequency spec; enables fast system boot in telecom and networking equipment |
| Phase Jitter (1.875–20 MHz) | 0.25–0.35 ps RMS - measured at 156.25 MHz reference; ensures clean sampling edges for high-speed SerDes and ADC clocking |
| Operating Temperature | –40 to +85 °C - qualified per MIL-STD-883 thermal shock/vibration tests; suitable for uncontrolled industrial enclosures |
Pinout & Package
Package: 5 × 7 mm, 4-pin SMD (CLCC-style), RoHS-compliant, Pb-free, gold-over-nickel contact pads. Industry-standard footprint per IPC-7351; compatible with JEDEC J-STD-020E reflow profile.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | OE | Output Enable (active high); internal pull-up resistor (45 kΩ) eliminates need for external bias; controls tristate behavior with <20 µs enable time |
| 2 | GND | Electrical and case ground; dedicated low-impedance return path for clock signal integrity and EMI reduction |
| 3 | CLK | CMOS clock output; 0.45–1.2 ns rise/fall time into 15 pF load; 48–52% duty cycle ensures balanced setup/hold margins |
| 4 | VDD | 3.3 V power input; supplies internal LDO and DSPLL core; requires local 100 nF ceramic decoupling per datasheet layout guidelines |
Key Features
| Feature | Design Value |
|---|---|
| DSPLL® Any-Frequency Synthesis | Generates exact 25.000000 MHz from fixed crystal - eliminates custom crystal procurement, reduces BOM count, and guarantees long-term frequency repeatability |
| On-Chip LDO Regulator | Filters supply noise up to 1 MHz; maintains <1 ps RMS jitter degradation even with 100 mVPP ripple on VDD - critical for mixed-signal SoC timing |
| Production-Tested Crystal ESR & DLD | Each unit undergoes individual crystal resonance validation; ensures 100% reliability margin against aging, shock, and thermal cycling failure modes |
| Runt Suppression | Eliminates false clock edges during power-up and OE assertion; prevents metastability in downstream flip-flops and state machines |
| Factory-Programmed Configuration | No field programming needed - shipped fully calibrated for 25 MHz, 3.3 V, CMOS, ±30 ppm, –40 to +85 °C - cuts NRE and lead time vs. custom XOs |
Applications
| FPGA Clock Generation | Gigabit Ethernet PHY Timing |
|---|---|
Use Scenario: Provides primary reference clock to Xilinx Artix-7 or Intel Cyclone V FPGA fabric and transceivers in industrial control gateways. IC Role / Device Role / Timing Role: System master clock source; synchronizes logic fabric, memory interfaces, and 1.25 Gbps GMII/RGMII data paths. Use Value: ±30 ppm stability and <0.35 ps RMS phase jitter ensure reliable setup/hold timing closure and low BER in SERDES links. | Use Scenario: Supplies 25 MHz reference to Broadcom BCM54213 or Marvell Alaska 88E1512 Gigabit Ethernet PHYs in switch/router line cards. IC Role / Device Role / Timing Role: PHY reference oscillator; drives MDIO interface and internal PLLs for 125 MHz PMA clock generation. Use Value: Runt suppression and fast 10 ms startup guarantee deterministic PHY initialization during hot-swap or reboot sequences. |
| Telecom Line Card Timing | Industrial PLC Real-Time Clock |
Use Scenario: Delivers stable 25 MHz clock to TI TMS320C6678 DSPs and ADI AD9528 clock distributors in LTE baseband units. IC Role / Device Role / Timing Role: Primary timing reference for multi-core DSP clusters and JESD204B converter synchronization. Use Value: Total stability including 10-year aging enables 15+ year field deployment without recalibration or drift-related service calls. | Use Scenario: Serves as RTC oscillator for Siemens SIMATIC S7-1500 controllers and Beckhoff CX9020 embedded PCs in factory automation systems. IC Role / Device Role / Timing Role: High-accuracy timebase for real-time task scheduling, motion control loops, and timestamped I/O logging. Use Value: –40 to +85 °C operation and MIL-STD-883 qualification ensure continuous uptime in unconditioned cabinet environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar crystal oscillator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si510CBA25M0000AAG | Same family, identical specs - baseline reference | N/A | Default selection for new designs requiring proven 5×7 mm CMOS XO with 3.3 V and ±30 ppm |
| ABM8G-25.000MHZ-18-D2Y-T | Standard quartz XO (no DSPLL); ±50 ppm total stability; 3.3 V CMOS; 5×7 mm; no OE pin or LDO | Lacks output enable, supply noise rejection, and aging compensation - unsuitable for high-reliability or noisy-rail systems | Select only if cost sensitivity outweighs jitter, stability, and feature requirements; verify 50 ppm meets system timing budget |
Compared with ABM8G-25.000MHZ-18-D2Y-T, the 510CBA25M0000AAG delivers 20 ppm tighter stability, integrated noise filtering, and programmable output control - making it preferable for telecom, industrial, and high-speed digital systems where timing margin is constrained.
Availability
510CBA25M0000AAG is available at Aetrix Electronics and suitable for FPGA clock generation, Gigabit Ethernet PHY timing, and telecom line card timing requiring stable component supply, long-lifecycle support, and guaranteed factory calibration.
Supply support for 510CBA25M0000AAG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs.
The Si510/511 XO product line was designed to replace legacy crystal oscillators with digitally programmable, high-stability timing sources for networking, telecom, and computing infrastructure - emphasizing reliability, noise immunity, and rapid customization.
FAQ
What is the nominal output frequency of the 510CBA25M0000AAG?
The 510CBA25M0000AAG is factory-programmed to deliver an exact 25.000000 MHz CMOS clock output. This frequency is fixed at time of manufacture and cannot be adjusted in-circuit. It is validated across –40 to +85 °C and meets ±30 ppm total stability including 10-year aging, making it suitable for precision timing applications such as FPGA configuration clocks and Ethernet PHY references.
Does the 510CBA25M0000AAG support output enable functionality?
Yes, the 510CBA25M0000AAG includes an active-high Output Enable (OE) pin on Pin 1 with an internal 45 kΩ pull-up resistor. When OE is high, the CLK output is active; when OE is low, the output enters high-impedance state. Enable and disable times are ≤20 µs and ≤5 µs respectively for frequencies ≥10 MHz, ensuring clean, glitch-free control in power-managed systems.
What supply voltage does the 510CBA25M0000AAG require?
The 510CBA25M0000AAG is configured for 3.3 V operation (±10%), as indicated by the "C" in its part number. It integrates an on-chip LDO regulator that filters supply noise and maintains low jitter performance even with up to 100 mVPP ripple on VDD. External decoupling with a 100 nF ceramic capacitor near Pin 4 is required per Skyworks layout guidelines.
Is the 510CBA25M0000AAG pin-compatible with other Si510 variants?
Yes - the 510CBA25M0000AAG uses the standard Si510 4-pin CMOS pinout (OE, GND, CLK, VDD) in the 5 × 7 mm package. It shares identical mechanical footprint and land pattern with all Si510 4-pin variants, enabling direct substitution within the same output format and voltage family. However, LVDS/LVPECL variants use 6-pin layouts and are not pin-compatible.
What is the startup time specification for the 510CBA25M0000AAG?
The 510CBA25M0000AAG has a maximum startup time of 10 ms - defined as the interval from application of minimum valid VDD until the CLK output reaches and remains within its specified frequency tolerance. This parameter is production-tested and guaranteed across –40 to +85 °C, supporting fast-boot requirements in telecom and industrial control systems.
510CBA25M0000AAG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- Si510
- Package/Case:
- 4-SMD, No Lead
- Packaging:
- Strip
- Product Status:
- Active
- Base Resonator:
- Crystal
- Type:
- XO (Standard)
- Frequency:
- 25 MHz
- Function:
- Enable/Disable
- Output:
- CMOS
- Voltage - Supply:
- 3.3V
- Frequency Stability:
- ±25ppm
- Absolute Pull Range (APR):
- -
- Operating Temperature:
- -40°C ~ 85°C
- Spread Spectrum Bandwidth:
- -
- Current - Supply (Max):
- 26mA
- Ratings:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- -
- Size / Dimension:
- 0.276" L x 0.197" W (7.00mm x 5.00mm)
- Height - Seated (Max):
- 0.071" (1.80mm)
510CBA25M0000AAG FAQ
1.How can I place an order for 510CBA25M0000AAG through Aetrix?
Please submit a Request for Quotation (RFQ) for 510CBA25M0000AAG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 510CBA25M0000AAG reliable?
The price and inventory of 510CBA25M0000AAG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 510CBA25M0000AAG is usually 5 days.
3.What payment methods are accepted for 510CBA25M0000AAG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 510CBA25M0000AAG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 510CBA25M0000AAG?
510CBA25M0000AAG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 510CBA25M0000AAG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 510CBA25M0000AAG?
For technical support, including 510CBA25M0000AAG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 510CBA25M0000AAG requirements.
6.How does Aetrix verify that 510CBA25M0000AAG is sourced from the original manufacturer or authorized distributors?
All 510CBA25M0000AAG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 510CBA25M0000AAG meets industry standards.
7.What is the process for return or replacement of 510CBA25M0000AAG?
All 510CBA25M0000AAG units undergo pre-shipment inspection (PSI). If there is an issue with 510CBA25M0000AAG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 510CBA25M0000AAG part is unused and in its original packaging.
Return procedure for 510CBA25M0000AAG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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