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Skyworks Solutions Inc. 510KBA125M000BAGR

Name: 510KBA125M000BAGR
Brand: Skyworks Solutions Inc.
SKU: 510KBA125M000BAGR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 510KBA125M000BAGR

Manufacturer:: Skyworks Solutions Inc.

Category:: Oscillators

Package:: 4-SMD, No Lead

Datasheet:: 510KBA125M000BAGR.pdf

Description:: XTAL OSC XO 125.0000MHZ CMOS SMD

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Product details

Overview

510KBA125M000BAGR from Skyworks Solutions is a factory-programmed, low-jitter crystal oscillator (XO) delivering 125.000 MHz output with ±30 ppm total stability (including 10-year aging), 3.3 V supply, LVDS output format, and operation across –40 °C to +85 °C in a 5 × 7 mm surface-mount package. It serves as a precision clock source for high-speed serial interfaces requiring deterministic timing.

For engineers reviewing the 510KBA125M000BAGR datasheet, 510KBA125M000BAGR pinout, 510KBA125M000BAGR application, or 510KBA125M000BAGR equivalent, this device offers DSPLL-based frequency synthesis, integrated LDO noise filtering, OE-controlled output enable/disable, and production-tested crystal ESR/DLD - critical for PCIe Gen3/4, Gigabit Ethernet PHYs, and FPGA reference clocks.

Technical Context

The 510KBA125M000BAGR implements Skyworks' DSPLL architecture with a fixed internal crystal and digital synthesizer, enabling exact 125.000 MHz generation without custom crystal tuning. Its LVDS output delivers 0.25–0.45 V_PPSE swing into 100 Ω differential termination with 48–52% duty cycle.

It integrates an on-chip LDO regulator for supply noise rejection (3.5 ps RMS jitter increase at 1 MHz VDD noise), supports active-high OE with internal pull-up, and guarantees startup time ≤10 ms and enable time ≤20 µs (f_O ≥10 MHz). Total stability includes initial accuracy, temperature, voltage, load, shock/vibration, and 10-year aging at 40 °C.

Key Specifications

Parameter	Value and Actual Design Meaning
Nominal Frequency	125.000 MHz - precisely programmed for PCIe reference clock, SDI pixel clock, or Ethernet MAC timing.
Output Format	LVDS - differential signaling with 0.25–0.45 V_PPSE, 100 Ω termination, enabling noise-immune board-level distribution.
Total Stability	±30 ppm - covers initial tolerance, –40 to +85 °C drift, supply/load variation, and 10-year aging, eliminating field recalibration.
Supply Voltage	3.3 V ±10% - compatible with standard logic rails; internal LDO filters supply noise to maintain low jitter.
Phase Jitter (1.875–20 MHz)	0.25–0.55 ps RMS - meets stringent requirements for 10G/25G SerDes PLLs and high-resolution ADC sampling clocks.
Operating Temperature	–40 °C to +85 °C - qualified for industrial and telecom infrastructure environments without derating.
Package	5 × 7 mm, 6-pin SMD - industry-standard footprint with CLK+, CLK−, VDD, GND, OE, and NC pins.

Pinout & Package

510KBA125M000BAGR uses a 6-pin, 5 × 7 mm surface-mount ceramic package (CLCC) with exposed pad. Pin 1 = NC, Pin 2 = OE (active-high, internal pull-up), Pin 3 = GND, Pin 4 = CLK+, Pin 5 = CLK−, Pin 6 = VDD.

Pin/Terminal	Circuit Role	Design Meaning
1	No Connect (NC)	Internally unconnected; must remain floating - no external tie required.
2	Output Enable (OE)	Active-high control: drives outputs to high-impedance when low; internal pull-up ensures safe default-on behavior.
3	GND	Electrical and case ground reference for all internal circuitry and output drivers.
4	CLK+	Positive LVDS output terminal; requires 100 Ω differential termination to CLK−.
5	CLK−	Negative LVDS output terminal; forms differential pair with CLK+ for common-mode noise rejection.
6	VDD	3.3 V power input; feeds internal LDO regulator that isolates clock core from supply ripple.

Key Features

Feature	Design Value
DSPLL Any-Frequency Synthesis	Generates exact 125.000 MHz from fixed crystal + digital synthesizer - eliminates custom crystal NRE and long lead times.
Integrated LDO Regulator	Provides >30 dB supply noise rejection; limits jitter degradation to ≤3.5 ps RMS under 100 mV_PP VDD noise.
Production-Tested Crystal ESR & DLD	Each unit undergoes individual crystal ESR and drive-level dependency screening - ensures long-term reliability and stability margin.
Runt Suppression	Prevents partial-clock pulses during power-up and OE transitions - avoids metastability in downstream synchronizers.
RoHS-Compliant, Pb-Free Packaging	Meets JEDEC J-STD-020E reflow profile (260 °C peak); compatible with automated SMT assembly and IPC-7351 land patterns.

Applications

PCIe Gen3/Gen4 Reference Clock	Gigabit Ethernet PHY Timing
Use Scenario: Provides 100/125 MHz reference clock to PCIe root complex or endpoint controllers in servers and switches. IC Role / Device Role / Timing Role: Primary system clock source meeting PCIe CEM specification jitter limits (≤1.0 ps RMS, 1.875–20 MHz). Use Value: DSPLL architecture and LVDS output ensure jitter remains within spec even under noisy 3.3 V rail conditions.	Use Scenario: Supplies 125 MHz clock to 1000BASE-X or SGMII PHYs in enterprise routers and optical transceivers. IC Role / Device Role / Timing Role: Low-phase-noise LVDS oscillator synchronized to IEEE 802.3 clause 49 requirements. Use Value: ±30 ppm total stability over temperature and life guarantees link training success and BER compliance.
FPGA/ASIC Configuration Clock	HD-SDI/3G-SDI Pixel Clock
Use Scenario: Drives configuration and I/O clock domains of Xilinx Versal or Intel Agilex FPGAs in broadcast and test equipment. IC Role / Device Role / Timing Role: High-integrity CMOS/LVDS clock source for bitstream loading and high-speed transceiver reference. Use Value: Runt suppression and fast enable time (<20 µs) prevent configuration errors during hot-plug or reset sequences.	Use Scenario: Generates 148.5 MHz or 125.000 MHz pixel clock for HD-SDI/3G-SDI serializers in video production switchers. IC Role / Device Role / Timing Role: Precision timing reference meeting SMPTE ST 292/424 jitter masks. Use Value: 0.25 ps RMS phase jitter (1.875–20 MHz) exceeds SMPTE's 0.3 ps requirement, ensuring clean eye diagrams.

PCIe Gen3/Gen4 Reference Clock

Gigabit Ethernet PHY Timing

Use Scenario: Provides 100/125 MHz reference clock to PCIe root complex or endpoint controllers in servers and switches.

IC Role / Device Role / Timing Role: Primary system clock source meeting PCIe CEM specification jitter limits (≤1.0 ps RMS, 1.875–20 MHz).

Use Value: DSPLL architecture and LVDS output ensure jitter remains within spec even under noisy 3.3 V rail conditions.

Use Scenario: Supplies 125 MHz clock to 1000BASE-X or SGMII PHYs in enterprise routers and optical transceivers.

IC Role / Device Role / Timing Role: Low-phase-noise LVDS oscillator synchronized to IEEE 802.3 clause 49 requirements.

Use Value: ±30 ppm total stability over temperature and life guarantees link training success and BER compliance.

FPGA/ASIC Configuration Clock

HD-SDI/3G-SDI Pixel Clock

Use Scenario: Drives configuration and I/O clock domains of Xilinx Versal or Intel Agilex FPGAs in broadcast and test equipment.

IC Role / Device Role / Timing Role: High-integrity CMOS/LVDS clock source for bitstream loading and high-speed transceiver reference.

Use Value: Runt suppression and fast enable time (<20 µs) prevent configuration errors during hot-plug or reset sequences.

Use Scenario: Generates 148.5 MHz or 125.000 MHz pixel clock for HD-SDI/3G-SDI serializers in video production switchers.

IC Role / Device Role / Timing Role: Precision timing reference meeting SMPTE ST 292/424 jitter masks.

Use Value: 0.25 ps RMS phase jitter (1.875–20 MHz) exceeds SMPTE's 0.3 ps requirement, ensuring clean eye diagrams.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock oscillator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si510KBA125M000AAG	Same Si510 family, identical 125 MHz/±30 ppm/LVDS spec, but in 3.2 × 5 mm package (vs. 5 × 7 mm).	Requires PCB layout change due to smaller footprint and different pinout (OE on Pin 1, NC on Pin 2).	Select for space-constrained designs where 3.2 × 5 mm is preferred and pin compatibility is verified.
AK2-125.000MHZ-EFE	125 MHz LVDS XO, ±25 ppm temp stability only (no 10-yr aging included), higher typical phase jitter (0.65 ps RMS).	Lacks full total stability guarantee; not suitable for long-life telecom deployments requiring aging margin.	Consider for cost-sensitive, shorter-lifecycle consumer applications where ±25 ppm temp stability suffices.

Compared with Si510KBA125M000AAG, 510KBA125M000BAGR offers larger thermal mass and proven manufacturability in 5 × 7 mm sockets; versus AK2-125.000MHZ-EFE, it delivers tighter total stability and lower jitter essential for high-reliability infrastructure.

Availability

510KBA125M000BAGR is available at Aetrix Electronics and suitable for PCIe reference clocking, Gigabit Ethernet PHY timing, and FPGA configuration requiring stable component supply, consistent parametric performance, and RoHS-compliant sourcing.

Supply support for 510KBA125M000BAGR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with design centers worldwide.

The Si510/511 family was engineered to replace legacy XOs with programmable, high-stability, low-jitter oscillators for datacenter, telecom, and broadcast systems demanding precise, reliable clocking without custom crystal delays.

FAQ

What output format and supply voltage does the 510KBA125M000BAGR use?

The 510KBA125M000BAGR is configured for LVDS output and 3.3 V supply, as indicated by the "KB" in its part number (K = 3.3 V, B = LVDS). It delivers differential 125.000 MHz signals with 0.25–0.45 V_PPSE swing into 100 Ω termination and operates across 2.97–3.63 V with internal LDO regulation.

Does the 510KBA125M000BAGR include aging compensation in its stability specification?

Yes, the ±30 ppm total stability rating for 510KBA125M000BAGR explicitly includes 10-year aging at 40 °C, along with initial accuracy, temperature drift, supply/load variation, and mechanical stress effects - per Skyworks' datasheet Table 2 note.

What is the pin configuration and OE polarity of the 510KBA125M000BAGR?

The 510KBA125M000BAGR uses a 6-pin 5 × 7 mm package with Pin 1 = NC, Pin 2 = OE (active-high, internal pull-up), Pin 3 = GND, Pin 4 = CLK+, Pin 5 = CLK−, Pin 6 = VDD. OE polarity is active-high, meaning outputs are enabled when OE ≥0.8 × VDD.

How does the DSPLL architecture in the 510KBA125M000BAGR improve reliability over traditional XOs?

The 510KBA125M000BAGR uses a fixed crystal with DSPLL synthesis instead of frequency-specific crystals. This eliminates crystal-to-crystal variability, enables full production testing of ESR and DLD per unit, and improves mechanical robustness - resulting in higher MTBF and tighter long-term stability than fundamental-mode XOs.

Can the 510KBA125M000BAGR be used in place of a 125 MHz fundamental-mode crystal oscillator?

No - the 510KBA125M000BAGR is a complete oscillator module (XO), not a crystal. It replaces both crystal + buffer ICs. It requires no external load capacitors or loop filter components and provides ready-to-use LVDS clock signals, simplifying layout and reducing BOM count versus discrete crystal + clock buffer solutions.

510KBA125M000BAGR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: Si510

Package/Case:: 4-SMD, No Lead

Packaging:: Tape & Reel (TR)

Product Status:: Active

Base Resonator:: Crystal

Type:: XO (Standard)

Frequency:: 125 MHz

Function:: Enable/Disable

Output:: CMOS

Voltage - Supply:: 1.8V

Frequency Stability:: ±25ppm

Absolute Pull Range (APR):: -

Operating Temperature:: -40°C ~ 85°C

Spread Spectrum Bandwidth:: -

Current - Supply (Max):: 26mA

Ratings:: -

Mounting Type:: Surface Mount

Supplier Device Package:: -

Size / Dimension:: 0.197" L x 0.126" W (5.00mm x 3.20mm)

Height - Seated (Max):: 0.050" (1.28mm)

510KBA125M000BAGR FAQ

1.How can I place an order for 510KBA125M000BAGR through Aetrix?

Please submit a Request for Quotation (RFQ) for 510KBA125M000BAGR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 510KBA125M000BAGR reliable?

The price and inventory of 510KBA125M000BAGR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 510KBA125M000BAGR is usually 5 days.

3.What payment methods are accepted for 510KBA125M000BAGR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 510KBA125M000BAGR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 510KBA125M000BAGR?

510KBA125M000BAGR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 510KBA125M000BAGR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 510KBA125M000BAGR?

For technical support, including 510KBA125M000BAGR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 510KBA125M000BAGR requirements.

6.How does Aetrix verify that 510KBA125M000BAGR is sourced from the original manufacturer or authorized distributors?

All 510KBA125M000BAGR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 510KBA125M000BAGR meets industry standards.

7.What is the process for return or replacement of 510KBA125M000BAGR?

All 510KBA125M000BAGR units undergo pre-shipment inspection (PSI). If there is an issue with 510KBA125M000BAGR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 510KBA125M000BAGR part is unused and in its original packaging.

Return procedure for 510KBA125M000BAGR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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