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Home > Products > Crystals, Oscillators, Resonators > Oscillators

Skyworks Solutions Inc. 510NBA125M000BAG

Name: 510NBA125M000BAG
Brand: Skyworks Solutions Inc.
SKU: 510NBA125M000BAG
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 510NBA125M000BAG

Manufacturer:: Skyworks Solutions Inc.

Category:: Oscillators

Package:: 6-SMD, No Lead

Datasheet:: 510NBA125M000BAG.pdf

Description:: XTAL OSC XO 125.0000MHZ CMOS SMD

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Product details

Overview

510NBA125M000BAG from Skyworks Solutions is a factory-programmed, low-jitter silicon-based crystal oscillator (XO) delivering 125.000 MHz output with ±30 ppm total stability over –40°C to +85°C, 3.3 V supply, and LVDS differential output in a 5 × 7 mm surface-mount package. It serves as a high-reliability clock source for FPGA/ASIC timing, PCIe Gen1–3, and Gigabit Ethernet PHYs.

For engineers reviewing the 510NBA125M000BAG datasheet, 510NBA125M000BAG pinout, 510NBA125M000BAG application, or 510NBA125M000BAG equivalent, this device offers DSPLL-based frequency flexibility, integrated LDO noise filtering, runt suppression on OE/power-up, and production-tested crystal ESR/DLD - critical for low-phase-noise, high-availability systems.

Technical Context

The 510NBA125M000BAG implements Skyworks' DSPLL architecture with a fixed internal crystal and digital synthesis, enabling precise 125.000 MHz generation without custom crystals. Its LVDS output operates at 3.3 V with 0.25–0.55 ps RMS phase jitter (1.875–20 MHz integration) and 48–52% duty cycle.

It features an on-chip LDO regulator for supply noise rejection, active-high OE with internal pull-up, and startup time ≤10 ms. The device supports tristate disable with ≤5 µs disable time (≥10 MHz), and meets MIL-STD-883 mechanical shock/vibration requirements.

Key Specifications

Parameter	Value and Actual Design Meaning
Nominal Frequency	125.000 MHz - precisely programmable for PCIe reference clocks and Ethernet line-rate timing.
Output Format	LVDS - differential signaling enables noise immunity and <18 ps pk-pk period jitter in noisy PCB environments.
Total Stability	±30 ppm - includes initial accuracy, temp, voltage, load, aging (10-year), ensuring long-term system timing margin.
Supply Voltage	3.3 V ±10% - compatible with standard logic rails; internal LDO filters supply ripple to preserve jitter performance.
Operating Temp	–40°C to +85°C - industrial-grade thermal range suitable for telecom infrastructure and embedded networking gear.
Package	5 × 7 mm, 6-pin SMD - industry-standard footprint with CLK+/CLK–, OE, VDD, GND, and NC pins; RoHS-compliant.
Phase Jitter (RMS)	0.25 ps (typ) - measured 1.875–20 MHz; meets stringent SerDes reference clock requirements for Gen3+ interfaces.

Pinout & Package

510NBA125M000BAG uses the Si510 6-pin 5 × 7 mm package with LVDS/LVPECL/HCSL configuration (OE on pin 2). Pin 1 is NC; pin 2 is OE (active-high, internal pull-up); pin 3 is GND; pin 4 is CLK+; pin 5 is CLK–; pin 6 is VDD.

Pin/Terminal	Circuit Role	Design Meaning
1	No Connect (NC)	Must remain unconnected; no internal circuitry attached - avoids unintended coupling or ESD paths.
2	Output Enable (OE)	Active-high control; internal 45 kΩ pull-up ensures defined state at power-up; enables fast (<20 µs) output enable/disable.
3	GND	Electrical and case ground reference; requires low-inductance connection to minimize ground bounce and jitter.
4	CLK+	LVDS positive clock output; 100 Ω differential termination required for specified swing (0.25–0.45 V_PPSE) and symmetry.
5	CLK–	LVDS complementary clock output; matched trace length and impedance critical to maintain <1% duty cycle deviation.
6	VDD	3.3 V supply input; filtered by on-chip LDO - decoupling capacitor (0.1 µF + 10 µF) required per datasheet layout guidelines.

Key Features

Feature	Design Value
DSPLL Synthesis	Enables exact 125.000 MHz without custom crystal - reduces BOM count and eliminates crystal qualification delays.
On-Chip LDO Regulator	Provides >30 dB supply noise rejection at 100–500 kHz - maintains sub-0.5 ps jitter even with noisy 3.3 V rails.
Runt Suppression	Eliminates false clock edges during power-up and OE transitions - prevents metastability in synchronous logic.
Production-Tested Crystal ESR/DLD	Guarantees long-term reliability and stability margin - no field failures due to crystal degradation over 10 years.
Industry-Standard 5×7 mm Package	Drop-in compatible with legacy XO footprints - no PCB redesign needed when upgrading from quartz-based oscillators.

Applications

PCIe Reference Clock	Gigabit Ethernet PHY
Use Scenario: Providing the 100 MHz or 125 MHz reference clock to PCIe root complex or endpoint controllers in servers and switches. IC Role / Device Role / Timing Role: Primary low-jitter system clock generator synchronized to PCIe specification timing budgets. Use Value: 0.25 ps RMS phase jitter ensures compliance with PCIe Gen3 eye diagram mask and reduces bit error rate in high-speed serial links.	Use Scenario: Driving the 125 MHz clock input of 1000BASE-X or SGMII PHYs in enterprise routers and industrial gateways. IC Role / Device Role / Timing Role: Differential LVDS clock source meeting IEEE 802.3 clause 49 jitter limits for fiber/copper physical layers. Use Value: ±30 ppm total stability guarantees link training success across temperature and aging - no manual recalibration required.
FPGA Configuration Clock	Telecom Line Card Timing
Use Scenario: Supplying configuration and operation clock to Xilinx or Intel FPGAs used in packet processing and signal conditioning modules. IC Role / Device Role / Timing Role: Single-ended or differential clock source for FPGA I/O banks, transceivers, and logic fabric. Use Value: Factory-programmed 125.000 MHz eliminates external PLL setup; DSPLL architecture avoids loop bandwidth tuning complexity.	Use Scenario: Generating primary timing for TDM-over-IP or CPRI fronthaul interfaces in 4G/5G base station line cards. IC Role / Device Role / Timing Role: Stratum-3–equivalent oscillator providing holdover-stable clock for synchronization distribution. Use Value: 10-year aging included in ±30 ppm spec enables >7-year field deployment without timing drift-induced service interruption.

PCIe Reference Clock

Gigabit Ethernet PHY

Use Scenario: Providing the 100 MHz or 125 MHz reference clock to PCIe root complex or endpoint controllers in servers and switches.

IC Role / Device Role / Timing Role: Primary low-jitter system clock generator synchronized to PCIe specification timing budgets.

Use Value: 0.25 ps RMS phase jitter ensures compliance with PCIe Gen3 eye diagram mask and reduces bit error rate in high-speed serial links.

Use Scenario: Driving the 125 MHz clock input of 1000BASE-X or SGMII PHYs in enterprise routers and industrial gateways.

IC Role / Device Role / Timing Role: Differential LVDS clock source meeting IEEE 802.3 clause 49 jitter limits for fiber/copper physical layers.

Use Value: ±30 ppm total stability guarantees link training success across temperature and aging - no manual recalibration required.

FPGA Configuration Clock

Telecom Line Card Timing

Use Scenario: Supplying configuration and operation clock to Xilinx or Intel FPGAs used in packet processing and signal conditioning modules.

IC Role / Device Role / Timing Role: Single-ended or differential clock source for FPGA I/O banks, transceivers, and logic fabric.

Use Value: Factory-programmed 125.000 MHz eliminates external PLL setup; DSPLL architecture avoids loop bandwidth tuning complexity.

Use Scenario: Generating primary timing for TDM-over-IP or CPRI fronthaul interfaces in 4G/5G base station line cards.

IC Role / Device Role / Timing Role: Stratum-3–equivalent oscillator providing holdover-stable clock for synchronization distribution.

Use Value: 10-year aging included in ±30 ppm spec enables >7-year field deployment without timing drift-induced service interruption.

Equivalent & Alternatives

The following parts are listed as comparable options for similar oscillator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si510NBA125M000AAG	Same 125 MHz, ±30 ppm, LVDS, but in 3.2 × 5 mm package - 30% smaller footprint, higher thermal resistance (164°C/W).	Better suited for space-constrained designs like pluggable optics or compact edge compute modules.	Select AAG if board area is critical and thermal derating is acceptable; verify PCB land pattern matches 3.2 × 5 mm 6-pin layout.
SG-8018CE 125.000000 MHz	Quartz-based LVDS XO; ±25 ppm temp stability only (no 10-yr aging); 2.5–3.3 V supply; 5 × 7 mm package.	Lacks DSPLL flexibility and integrated LDO - more sensitive to supply noise and less stable over lifetime.	Choose SG-8018CE only if cost is primary constraint and long-term aging margin is not required.

Compared with Si510NBA125M000AAG, the 510NBA125M000BAG offers lower thermal resistance (110°C/W vs. 164°C/W) and proven reliability in high-airflow telecom chassis; versus SG-8018CE, it delivers superior long-term stability and supply noise immunity via DSPLL + LDO architecture.

Availability

510NBA125M000BAG is available at Aetrix Electronics and suitable for PCIe reference clocking, Gigabit Ethernet PHY timing, and FPGA configuration requiring stable component supply across industrial temperature ranges and multi-year production cycles.

Supply support for 510NBA125M000BAG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of oscillator innovation.

The Si510/511 product line was designed to replace quartz XOs with programmable, high-reliability silicon timing devices for datacenter, networking, and telecom applications demanding low jitter and long-term stability.

FAQ

What output format and supply voltage does the 510NBA125M000BAG use?

The 510NBA125M000BAG is configured for LVDS output and 3.3 V supply, as indicated by the "B" (3.3 V LVDS) and "A" (±30 ppm) codes in its part number. It draws ≤23 mA typical supply current when enabled and supports tristate operation with ≤18 mA disabled current.

Does the 510NBA125M000BAG require external configuration or programming after soldering?

No. The 510NBA125M000BAG is factory-programmed with 125.000 MHz, LVDS output, ±30 ppm stability, active-high OE, and 3.3 V operation. No post-soldering configuration is needed - it begins operating within ≤10 ms of power application.

What is the meaning of "BAG" at the end of the 510NBA125M000BAG part number?

"BAG" denotes the package and temperature grade: "B" = 5 × 7 mm package, "A" = ±30 ppm total stability grade, "G" = –40°C to +85°C operating range. This matches Skyworks' official ordering syntax defined in the Si510/511 datasheet Rev. 1.4.

Can the 510NBA125M000BAG be used as a drop-in replacement for a quartz-based 125 MHz LVDS oscillator?

Yes - the 510NBA125M000BAG uses the same 5 × 7 mm, 6-pin footprint and pinout (CLK+/CLK–, OE, VDD, GND, NC) as standard LVDS XOs. Its DSPLL architecture provides identical electrical behavior while improving reliability and supply noise rejection.

What is the startup time and disable time specification for the 510NBA125M000BAG?

The 510NBA125M000BAG has a maximum startup time of 10 ms (from minimum VDD to output within frequency spec) and a disable time of ≤5 µs for frequencies ≥10 MHz. These values ensure rapid system initialization and clean clock gating in power-managed subsystems.

510NBA125M000BAG Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: Si510

Package/Case:: 6-SMD, No Lead

Packaging:: Strip

Product Status:: Active

Base Resonator:: Crystal

Type:: XO (Standard)

Frequency:: 125 MHz

Function:: Enable/Disable

Output:: CMOS

Voltage - Supply:: 3.3V

Frequency Stability:: ±25ppm

Absolute Pull Range (APR):: -

Operating Temperature:: -40°C ~ 85°C

Spread Spectrum Bandwidth:: -

Current - Supply (Max):: 26mA

Ratings:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 4-VDFN (3.2x2.5)

Size / Dimension:: 0.197" L x 0.126" W (5.00mm x 3.20mm)

Height - Seated (Max):: 0.052" (1.33mm)

510NBA125M000BAG FAQ

1.How can I place an order for 510NBA125M000BAG through Aetrix?

Please submit a Request for Quotation (RFQ) for 510NBA125M000BAG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 510NBA125M000BAG reliable?

The price and inventory of 510NBA125M000BAG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 510NBA125M000BAG is usually 5 days.

3.What payment methods are accepted for 510NBA125M000BAG?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 510NBA125M000BAG transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 510NBA125M000BAG?

510NBA125M000BAG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 510NBA125M000BAG order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 510NBA125M000BAG?

For technical support, including 510NBA125M000BAG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 510NBA125M000BAG requirements.

6.How does Aetrix verify that 510NBA125M000BAG is sourced from the original manufacturer or authorized distributors?

All 510NBA125M000BAG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 510NBA125M000BAG meets industry standards.

7.What is the process for return or replacement of 510NBA125M000BAG?

All 510NBA125M000BAG units undergo pre-shipment inspection (PSI). If there is an issue with 510NBA125M000BAG, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 510NBA125M000BAG part is unused and in its original packaging.

Return procedure for 510NBA125M000BAG:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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