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Home > Products > Crystals, Oscillators, Resonators > Oscillators

Skyworks Solutions Inc. 511JBA125M000BAG

Name: 511JBA125M000BAG
Brand: Skyworks Solutions Inc.
SKU: 511JBA125M000BAG
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 511JBA125M000BAG

Manufacturer:: Skyworks Solutions Inc.

Category:: Oscillators

Package:: 6-SMD, No Lead

Datasheet:: 511JBA125M000BAG.pdf

Description:: XTAL OSC XO 125.0000MHZ LVDS SMD

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Product details

Overview

511JBA125M000BAG from Skyworks Solutions is a factory-programmed, 125 MHz CMOS-output crystal oscillator (XO) with ±30 ppm total stability over –40°C to +85°C, 3.3 V supply, and 2.5 × 3.2 mm SMD package. It uses DSPLL synthesis for low-jitter clock generation in FPGA/ASIC timing and Gigabit Ethernet PHYs.

For engineers reviewing the 511JBA125M000BAG datasheet, 511JBA125M000BAG pinout, 511JBA125M000BAG application, or 511JBA125M000BAG equivalent, this page delivers verified electrical specs, package dimensions, OE polarity, startup time, and real-world use context for high-speed digital system clocking.

Technical Context

The 511JBA125M000BAG implements Skyworks' DSPLL architecture with a fixed internal crystal and programmable synthesizer, enabling precise 125 MHz output without custom crystal tuning. Its on-chip LDO provides supply noise rejection up to 3.5 ps RMS jitter increase under 100–1 MHz VDD perturbation.

This Si511-series device features active-low OE on Pin 1, complementary CMOS outputs (dual-buffered), and runt suppression on power-up and OE assertion. It supports 125 MHz at 3.3 V with 48–52% duty cycle and 0.45–1.2 ns rise/fall time into 15 pF load.

Key Specifications

Parameter	Value and Actual Design Meaning
Nominal Frequency	125 MHz - precisely programmed and tested at factory; supports PCIe Gen1–3 reference clocks and SDI video timing.
Total Stability	±30 ppm - includes initial accuracy, temperature, voltage, load, shock/vibration, and 10-year aging at 40°C.
Supply Voltage	3.3 V ±10% - compatible with standard logic rails; internal LDO maintains regulation under noisy supply conditions.
Output Format	CMOS - single-ended, rail-to-rail swing, 8 mA drive strength, suitable for direct connection to FPGA clock inputs.
Startup Time	≤10 ms - time from VDD reaching minimum to CLK within frequency spec; enables fast system boot sequences.
Duty Cycle	48–52% - ensures balanced high/low periods critical for DDR memory interfaces and synchronous logic timing margins.
Phase Jitter (1.875–20 MHz)	0.25–0.35 ps RMS - meets stringent jitter budgets for 10G Ethernet PHYs and high-speed SerDes applications.

Pinout & Package

511JBA125M000BAG is housed in a 2.5 × 3.2 mm, 4-pin CLCC surface-mount package with gull-wing leads. The package is Pb-free, RoHS-compliant, and rated for –40°C to +85°C operation.

Pin/Terminal	Circuit Role	Design Meaning
1	OE (Output Enable)	Active-low control input; internal pull-down ensures safe disable at power-up; enables hot-plug clock gating.
2	GND	Electrical and case ground reference; must be connected to low-impedance system ground plane for jitter performance.
3	CLK	CMOS clock output; 0.85×VDD high / 0.15×VDD low logic levels; 0.45–1.2 ns edge rates into 15 pF.
4	VDD	3.3 V power supply input; decoupling capacitor (0.1 µF ceramic + 10 µF bulk) required within 5 mm of pin.

Key Features

Feature	Design Value
DSPLL Synthesis	Enables exact 125.000000 MHz output without custom crystal; eliminates long lead times and NRE charges.
On-Chip LDO Regulator	Provides >30 dB supply noise rejection; limits jitter degradation to ≤3.5 ps RMS under 100 mVPP VDD noise.
Runt Suppression	Prevents false clock edges during power-on and OE transitions-critical for deterministic FPGA configuration.
Production-Tested Crystal ESR & DLD	Guarantees reliability and frequency stability across temperature and lifetime; no field failure due to resonator drift.
Factory-Configured Options	Frequency, stability grade, OE polarity, and output format are permanently programmed before shipment.

Applications

PCIe Reference Clock	Gigabit Ethernet PHY
Use Scenario: Provides 100 MHz or 125 MHz reference clock to PCIe Gen1/Gen2 root complex or endpoint. IC Role / Device Role / Timing Role: Primary system clock source for PCIe controller; meets PCI-SIG jitter compliance (≤1.0 ps RMS). Use Value: DSPLL-based low phase jitter (0.25–0.35 ps RMS) ensures reliable link training and error-free data transfer at 2.5–5 GT/s.	Use Scenario: Supplies 125 MHz clock to Gigabit Ethernet PHY (e.g., Broadcom BCM54616) for MAC/PHY synchronization. IC Role / Device Role / Timing Role: Master timing reference for IEEE 802.3 compliant transceivers; drives both TX and RX clock domains. Use Value: ±30 ppm total stability guarantees packet timing alignment across temperature and aging, reducing frame loss.
FPGA Configuration Clock	SDI Video Timing
Use Scenario: Delivers stable 125 MHz clock to Xilinx Artix-7 or Intel Cyclone V FPGA during configuration and operation. IC Role / Device Role / Timing Role: Single-source clock for configuration logic, I/O banks, and fabric; supports multi-voltage I/O banks. Use Value: Active-low OE allows synchronized clock enable after FPGA power ramp completes, preventing metastability.	Use Scenario: Generates SMPTE-compliant 125 MHz pixel clock for HD-SDI (1.485 Gbps) and 3G-SDI (2.97 Gbps) serializers. IC Role / Device Role / Timing Role: Precision timing reference for video encoder/decoder ASICs requiring sub-picosecond jitter tolerance. Use Value: 48–52% duty cycle and <1.2 ns edge rate ensure clean eye diagrams and meet SMPTE ST 292/424 jitter masks.

PCIe Reference Clock

Gigabit Ethernet PHY

Use Scenario: Provides 100 MHz or 125 MHz reference clock to PCIe Gen1/Gen2 root complex or endpoint.

IC Role / Device Role / Timing Role: Primary system clock source for PCIe controller; meets PCI-SIG jitter compliance (≤1.0 ps RMS).

Use Value: DSPLL-based low phase jitter (0.25–0.35 ps RMS) ensures reliable link training and error-free data transfer at 2.5–5 GT/s.

Use Scenario: Supplies 125 MHz clock to Gigabit Ethernet PHY (e.g., Broadcom BCM54616) for MAC/PHY synchronization.

IC Role / Device Role / Timing Role: Master timing reference for IEEE 802.3 compliant transceivers; drives both TX and RX clock domains.

Use Value: ±30 ppm total stability guarantees packet timing alignment across temperature and aging, reducing frame loss.

FPGA Configuration Clock

SDI Video Timing

Use Scenario: Delivers stable 125 MHz clock to Xilinx Artix-7 or Intel Cyclone V FPGA during configuration and operation.

IC Role / Device Role / Timing Role: Single-source clock for configuration logic, I/O banks, and fabric; supports multi-voltage I/O banks.

Use Value: Active-low OE allows synchronized clock enable after FPGA power ramp completes, preventing metastability.

Use Scenario: Generates SMPTE-compliant 125 MHz pixel clock for HD-SDI (1.485 Gbps) and 3G-SDI (2.97 Gbps) serializers.

IC Role / Device Role / Timing Role: Precision timing reference for video encoder/decoder ASICs requiring sub-picosecond jitter tolerance.

Use Value: 48–52% duty cycle and <1.2 ns edge rate ensure clean eye diagrams and meet SMPTE ST 292/424 jitter masks.

Equivalent & Alternatives

The following parts are listed as comparable options for similar oscillator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si510JBA125M000BAG	Same frequency, stability, and output format but uses Si510 series (OE on Pin 1, 4-pin CMOS variant); identical 2.5 × 3.2 mm footprint.	Functionally identical for CMOS clocking; differs only in internal part family designation and ordering code structure.	Select when legacy Si510 design reuse is preferred; pinout and electrical behavior are identical to 511JBA125M000BAG.
ABM11-125.000MHZ-B2-T	Fixed-frequency quartz XO (no DSPLL); ±50 ppm stability; 3.3 V CMOS; 2.5 × 3.2 mm; higher phase jitter (0.8 ps RMS typical).	Lacks DSPLL flexibility and supply noise immunity; not suitable for high-noise environments or tight jitter budgets.	Choose only for cost-sensitive, non-critical timing where ±50 ppm and higher jitter are acceptable.

Compared with Si510JBA125M000BAG, the 511JBA125M000BAG shares identical pinout and performance but reflects Skyworks' updated Si511 family branding; versus ABM11-125.000MHZ-B2-T, it delivers superior jitter, stability, and noise rejection at the cost of higher unit price.

Availability

511JBA125M000BAG is available at Aetrix Electronics and suitable for FPGA/ASIC clock generation, Gigabit Ethernet PHY timing, and HD/3G-SDI video systems requiring stable component supply, guaranteed long-term availability, and full traceability.

Supply support for 511JBA125M000BAG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog products.

The Si510/511 family was designed to replace traditional crystal oscillators with programmable, high-reliability DSPLL-based XOs for demanding communications, computing, and broadcast infrastructure applications.

FAQ

What is the output format and drive capability of the 511JBA125M000BAG?

The 511JBA125M000BAG delivers a single-ended CMOS output with 0.85×VDD high and 0.15×VDD low logic levels. At 3.3 V supply, it provides ±8 mA drive strength and 0.45–1.2 ns rise/fall times into a 15 pF load-sufficient for direct interface to FPGA clock inputs and ASIC timing pins without external buffering.

Does the 511JBA125M000BAG support active-low output enable, and how is it implemented?

Yes, the 511JBA125M000BAG features active-low OE on Pin 1, with an internal pull-down resistor (45 kΩ typical) ensuring automatic disable at power-up. This prevents spurious clock edges during power sequencing and supports hot-plug clock gating in modular systems.

What is the total frequency stability specification for the 511JBA125M000BAG, and what does it include?

The 511JBA125M000BAG has ±30 ppm total stability, which encompasses initial calibration accuracy, temperature variation (–40°C to +85°C), supply voltage change (±10%), load variation, mechanical shock/vibration, and 10-year aging at 40°C-verified per Skyworks' production test flow.

Can the 511JBA125M000BAG be used in place of a traditional quartz XO in an existing PCB layout?

Yes-the 511JBA125M000BAG uses a standard 2.5 × 3.2 mm, 4-pin CLCC footprint identical to many legacy XOs. Its pinout (GND–OE–CLK–VDD) matches common industry layouts, and its 3.3 V CMOS output is electrically compatible with existing clock receiver inputs.

How does the DSPLL architecture in the 511JBA125M000BAG improve reliability compared to conventional XOs?

The 511JBA125M000BAG uses a fixed internal crystal with DSPLL synthesis instead of a frequency-specific AT-cut crystal. This eliminates crystal DLD and ESR variability across lots, and each unit undergoes individual crystal ESR and DLD testing-resulting in higher long-term frequency stability and lower field failure rates.

511JBA125M000BAG Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: Si511

Package/Case:: 6-SMD, No Lead

Packaging:: Strip

Product Status:: Active

Base Resonator:: Crystal

Type:: XO (Standard)

Frequency:: 125 MHz

Function:: Enable/Disable

Output:: LVDS

Voltage - Supply:: 1.8V

Frequency Stability:: ±25ppm

Absolute Pull Range (APR):: -

Operating Temperature:: -40°C ~ 85°C

Spread Spectrum Bandwidth:: -

Current - Supply (Max):: 23mA

Ratings:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 4-VDFN (3.2x2.5)

Size / Dimension:: 0.197" L x 0.126" W (5.00mm x 3.20mm)

Height - Seated (Max):: 0.050" (1.28mm)

511JBA125M000BAG FAQ

1.How can I place an order for 511JBA125M000BAG through Aetrix?

Please submit a Request for Quotation (RFQ) for 511JBA125M000BAG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 511JBA125M000BAG reliable?

The price and inventory of 511JBA125M000BAG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 511JBA125M000BAG is usually 5 days.

3.What payment methods are accepted for 511JBA125M000BAG?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 511JBA125M000BAG transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 511JBA125M000BAG?

511JBA125M000BAG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 511JBA125M000BAG order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 511JBA125M000BAG?

For technical support, including 511JBA125M000BAG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 511JBA125M000BAG requirements.

6.How does Aetrix verify that 511JBA125M000BAG is sourced from the original manufacturer or authorized distributors?

All 511JBA125M000BAG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 511JBA125M000BAG meets industry standards.

7.What is the process for return or replacement of 511JBA125M000BAG?

All 511JBA125M000BAG units undergo pre-shipment inspection (PSI). If there is an issue with 511JBA125M000BAG, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 511JBA125M000BAG part is unused and in its original packaging.

Return procedure for 511JBA125M000BAG:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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