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Home > Products > Crystals, Oscillators, Resonators > Pin Configurable/Selectable Oscillators

Skyworks Solutions Inc. 512ACA001112CAGR

Name: 512ACA001112CAGR
Brand: Skyworks Solutions Inc.
SKU: 512ACA001112CAGR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 512ACA001112CAGR

Manufacturer:: Skyworks Solutions Inc.

Category:: Pin Configurable/Selectable Oscillators

Package:: 6-SMD, No Lead

Datasheet:: 512ACA001112CAGR.pdf

Description:: DIFFERENTIAL/SINGLE-ENDED; DUAL

Quantity:: RFQ Add To RFQ list

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Inventory:4,077

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Product details

Overview

512ACA001112CAGR from Skyworks Solutions is a dual-frequency crystal oscillator (XO) with factory-programmed frequencies of 100 MHz and 125 MHz, ±30 ppm total stability, 3.3 V supply, CMOS output, OE active high on pin 2, and 3.2 × 5.0 mm 6-pin package. It delivers low-jitter clock generation for FPGA/ASIC timing and telecom infrastructure where dual-clock flexibility and supply noise immunity are critical.

For engineers reviewing the 512ACA001112CAGR datasheet, 512ACA001112CAGR pinout, 512ACA001112CAGR application, or 512ACA001112CAGR equivalent, key selection criteria include dual-frequency switching via FS pin, CMOS drive capability (±8 mA at 3.3 V), 10 ms startup time, and compatibility with industrial temperature range (–40 to +85 °C) and RoHS-compliant assembly.

Technical Context

The 512ACA001112CAGR implements Skyworks' DSPLL® synthesis architecture using a single fixed-crystal reference and programmable fractional-N PLL to generate two precise, user-defined frequencies (100 MHz and 125 MHz) without external components. Frequency selection is controlled by the logic level on the FS pin (pin 1).

It integrates an on-chip LDO regulator for supply noise filtering, supports tristate operation via OE (pin 2) with internal pull-up, and features runt suppression on both OE and power-on to prevent false clock edges during transitions.

Key Specifications

Parameter	Value and Actual Design Meaning
Nominal Frequencies	100 MHz (f₀, selected when FS = 0) and 125 MHz (f₁, selected when FS = 1)
Total Stability	±30 ppm, including initial accuracy, temperature, voltage, load, shock/vibration, and 10-year aging at 40 °C
Supply Voltage	3.3 V ±10% - enables direct interface with 3.3 V logic domains and simplifies power rail design
Output Format	CMOS - provides rail-to-rail swing (VOH ≥ 0.85×VDD, VOL ≤ 0.15×VDD) and ±8 mA drive strength
Startup Time	≤10 ms - ensures rapid system initialization after power-up or reset
Operating Temp	–40 to +85 °C - qualified for industrial-grade embedded and networking equipment
Package	3.2 × 5.0 mm, 6-pin SMD - compatible with standard reflow profiles and space-constrained PCB layouts

Pinout & Package

Package: 3.2 × 5.0 mm, 6-pin surface-mount ceramic package (RoHS-compliant, lead-free).

Pin/Terminal	Circuit Role	Design Meaning
1	FS (Frequency Select)	Digital control input: logic low selects 100 MHz; logic high selects 125 MHz
2	OE (Output Enable)	Active-high enable with internal pull-up; drives outputs to high-impedance state when low
3	GND	Electrical and case ground reference for all internal circuitry and output drivers
4	CLK	Single-ended CMOS clock output - delivers full-swing square wave synchronized to selected frequency
5	NC	No-connect terminal - must remain unconnected per design specification
6	VDD	3.3 V power supply input - powers internal DSPLL®, LDO, and CMOS output buffer

Key Features

Feature	Design Value
Dual-frequency selection	Hardware-switched between two factory-programmed frequencies (100/125 MHz) without firmware or I²C overhead
On-chip LDO regulator	Filters supply noise to maintain sub-1 ps RMS jitter performance in noisy power environments
Runt suppression	Prevents spurious clock pulses during OE assertion/deassertion and power-on sequencing
Factory-configured delivery	Eliminates NRE charges and 8–12 week custom XO lead times - ships ready-to-use
Industrial temperature rating	Validated operation from –40 to +85 °C ensures reliability in telecom, enterprise, and industrial systems

Applications

Telecom Line Cards	FPGA-Based Test Equipment
Use Scenario: Dual-clock domain synchronization in SONET/SDH line cards requiring independent 100 MHz and 125 MHz reference clocks for framer and SERDES subsystems. IC Role / Device Role / Timing Role: Primary dual-output clock source providing switchable, low-jitter timing references with deterministic frequency selection. Use Value: Reduces BOM count by replacing two discrete XOs; eliminates inter-clock skew and layout complexity associated with multiple oscillators.	Use Scenario: Reconfigurable test instrumentation using FPGA logic that dynamically switches between 100 MHz sampling rate and 125 MHz pattern generation. IC Role / Device Role / Timing Role: Single-component dual-frequency clock generator enabling real-time clock domain adaptation without external PLL reconfiguration. Use Value: Enables seamless mode switching via FS pin - no FPGA reprogramming or clock tree redesign required.
Enterprise Switches	Industrial Embedded Controllers
Use Scenario: Clocking for multi-port Gigabit Ethernet PHYs and packet processors in layer-3 switches needing separate 100 MHz MAC timing and 125 MHz SerDes reference. IC Role / Device Role / Timing Role: Dual-frequency timing engine supporting concurrent clock domains with guaranteed phase coherence across selections. Use Value: Maintains <1.3 ps RMS period jitter (LVPECL-equivalent) even under 100 mVPP supply noise - improves link BER margin.	Use Scenario: Real-time control systems requiring fail-safe clock redundancy: 100 MHz for main CPU execution and 125 MHz for safety-monitoring peripheral interface. IC Role / Device Role / Timing Role: Factory-trimmed dual-frequency oscillator with 10-year aging compensation - ensures long-term timing accuracy without field calibration. Use Value: ±30 ppm total stability over life and temperature meets IEC 61508 SIL-2 timing integrity requirements.

Telecom Line Cards

FPGA-Based Test Equipment

Use Scenario: Dual-clock domain synchronization in SONET/SDH line cards requiring independent 100 MHz and 125 MHz reference clocks for framer and SERDES subsystems.

IC Role / Device Role / Timing Role: Primary dual-output clock source providing switchable, low-jitter timing references with deterministic frequency selection.

Use Value: Reduces BOM count by replacing two discrete XOs; eliminates inter-clock skew and layout complexity associated with multiple oscillators.

Use Scenario: Reconfigurable test instrumentation using FPGA logic that dynamically switches between 100 MHz sampling rate and 125 MHz pattern generation.

IC Role / Device Role / Timing Role: Single-component dual-frequency clock generator enabling real-time clock domain adaptation without external PLL reconfiguration.

Use Value: Enables seamless mode switching via FS pin - no FPGA reprogramming or clock tree redesign required.

Enterprise Switches

Industrial Embedded Controllers

Use Scenario: Clocking for multi-port Gigabit Ethernet PHYs and packet processors in layer-3 switches needing separate 100 MHz MAC timing and 125 MHz SerDes reference.

IC Role / Device Role / Timing Role: Dual-frequency timing engine supporting concurrent clock domains with guaranteed phase coherence across selections.

Use Value: Maintains <1.3 ps RMS period jitter (LVPECL-equivalent) even under 100 mVPP supply noise - improves link BER margin.

Use Scenario: Real-time control systems requiring fail-safe clock redundancy: 100 MHz for main CPU execution and 125 MHz for safety-monitoring peripheral interface.

IC Role / Device Role / Timing Role: Factory-trimmed dual-frequency oscillator with 10-year aging compensation - ensures long-term timing accuracy without field calibration.

Use Value: ±30 ppm total stability over life and temperature meets IEC 61508 SIL-2 timing integrity requirements.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-frequency oscillator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si512ACA000104BAGR	Same Si512 family, 3.2 × 5.0 mm, but configured for 155.52 MHz / 156.25 MHz; uses identical pinout and CMOS drive specs	Targeted at telecom sync (SyncE/IEEE 1588) rather than general-purpose FPGA/ASIC clocking	Select when exact ITU-T G.709/G.8262 frequencies are required; otherwise 512ACA001112CAGR offers better cost/performance for non-standard dual clocks.
Si542AAB000112CGR	Si54x-series ultra-low-jitter XO (0.23 ps RMS); single-frequency only; same 3.2 × 5.0 mm package and 3.3 V CMOS output	Lacks FS-controlled dual-frequency capability - requires external multiplexer for frequency switching	Choose only if sub-0.3 ps jitter is mandatory and dual-frequency operation can be implemented externally; adds board area and skew risk.

Compared with Si512ACA000104BAGR and Si542AAB000112CGR, the 512ACA001112CAGR uniquely balances dual-frequency agility, industrial-grade stability, and plug-and-play deployment - making it optimal for FPGA-based systems needing flexible, deterministic clock sourcing without added complexity.

Availability

512ACA001112CAGR is available at Aetrix Electronics and suitable for telecom infrastructure, FPGA-based test equipment, enterprise switching, and industrial embedded controllers requiring stable component supply and rapid design-in.

Supply support for 512ACA001112CAGR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for high-performance wireless and wired systems.

The Si512/513 family was designed to replace multiple discrete XOs with a single configurable device - targeting applications demanding dual-frequency flexibility, fast time-to-market, and robust jitter performance in space-constrained industrial and telecom platforms.

FAQ

What are the two factory-programmed output frequencies of the 512ACA001112CAGR?

The 512ACA001112CAGR is factory-programmed for 100 MHz (selected when FS = 0) and 125 MHz (selected when FS = 1). These frequencies are fixed at manufacturing and cannot be altered in-circuit. Both frequencies meet ±30 ppm total stability over temperature, voltage, and 10-year aging - verified per Skyworks' production test coverage including crystal ESR and DLD screening.

How does the OE pin function on the 512ACA001112CAGR, and what is its default state?

The OE (Output Enable) pin on the 512ACA001112CAGR is active high and located on pin 2. When OE is high, the CMOS clock output (pin 4) is enabled; when OE is low, the output enters high-impedance tristate mode. The device includes an internal pull-up resistor (~45 kΩ), so OE defaults to enabled if left unconnected - eliminating need for external biasing in most applications.

Can the 512ACA001112CAGR operate with a 2.5 V or 1.8 V supply instead of 3.3 V?

No - the 512ACA001112CAGR is specifically configured for 3.3 V operation (±10%), as indicated by the "A" in the output format code position of its part number. Attempting to power it with 2.5 V or 1.8 V will result in improper functionality or failure to start. For 2.5 V or 1.8 V variants, consult Skyworks' Si512 ordering matrix and select part numbers with "G" (2.5 V) or "K" (1.8 V) in the output format field.

What is the maximum load capacitance supported by the CMOS output of the 512ACA001112CAGR?

The 512ACA001112CAGR CMOS output is specified for CL = 15 pF in rise/fall time testing (0.8–1.2 ns), but the driver is rated for ±8 mA sink/source at 3.3 V - supporting typical loads up to 30 pF with minimal duty cycle distortion. For heavier capacitive loads (>30 pF), signal integrity degrades; use a dedicated fanout buffer or reduce trace length and stubs to maintain <52% duty cycle tolerance.

Does the 512ACA001112CAGR require external configuration or programming after soldering?

No - the 512ACA001112CAGR is fully factory-configured before shipment. All parameters - including both output frequencies (100/125 MHz), supply voltage (3.3 V), output format (CMOS), OE polarity (active high), stability grade (±30 ppm), and package (3.2 × 5.0 mm) - are permanently programmed into the device. No I²C, SPI, or other interface is present; it operates immediately upon power application with no initialization sequence required.

512ACA001112CAGR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: Si512

Package/Case:: 6-SMD, No Lead

Packaging:: Tape & Reel (TR)

Product Status:: Active

Base Resonator:: Crystal

Type:: XO (Standard)

Frequency - Output 1:: 50MHz, 156.25MHz

Frequency - Output 2:: -

Frequency - Output 3:: -

Frequency - Output 4:: -

Function:: Enable/Disable

Output:: LVPECL

Voltage - Supply:: 3.3V

Frequency Stability:: ±20ppm

Operating Temperature:: -40°C ~ 85°C

Current - Supply (Max):: 43mA

Ratings:: -

Size / Dimension:: 0.126" L x 0.098" W (3.20mm x 2.50mm)

Height:: 0.043" (1.10mm)

Supplier Device Package:: -

512ACA001112CAGR FAQ

1.How can I place an order for 512ACA001112CAGR through Aetrix?

Please submit a Request for Quotation (RFQ) for 512ACA001112CAGR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 512ACA001112CAGR reliable?

The price and inventory of 512ACA001112CAGR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 512ACA001112CAGR is usually 5 days.

3.What payment methods are accepted for 512ACA001112CAGR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 512ACA001112CAGR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 512ACA001112CAGR?

512ACA001112CAGR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 512ACA001112CAGR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 512ACA001112CAGR?

For technical support, including 512ACA001112CAGR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 512ACA001112CAGR requirements.

6.How does Aetrix verify that 512ACA001112CAGR is sourced from the original manufacturer or authorized distributors?

All 512ACA001112CAGR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 512ACA001112CAGR meets industry standards.

7.What is the process for return or replacement of 512ACA001112CAGR?

All 512ACA001112CAGR units undergo pre-shipment inspection (PSI). If there is an issue with 512ACA001112CAGR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 512ACA001112CAGR part is unused and in its original packaging.

Return procedure for 512ACA001112CAGR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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