Skyworks Solutions Inc. 512BBA000233BAG

Overview

512BBA000233BAG from Skyworks Solutions is a dual-frequency, factory-programmed crystal oscillator (XO) with CMOS output, 3.3 V supply, ±50 ppm total stability, and 2.5 × 3.2 mm package. It delivers two user-selectable frequencies-100 MHz and 125 MHz-with low-jitter performance (0.25–0.35 ps RMS phase jitter), fast enable/disable timing (≤20 µs/≤5 µs), and integrated runt suppression. It serves as a precision clock source in FPGA/ASIC timing, Gigabit Ethernet PHYs, and telecom line cards.

For engineers reviewing the 512BBA000233BAG datasheet, 512BBA000233BAG pinout, 512BBA000233BAG application, or 512BBA000233BAG equivalent, this page provides verified technical context, validated pin functions, confirmed dual-frequency switching behavior, real-world jitter metrics at 100/125 MHz, and direct alternative part comparisons for clock tree redesign or supply continuity planning.

Technical Context

The 512BBA000233BAG implements Skyworks' DSPLL® synthesis architecture, using a fixed internal crystal and digital PLL to generate any frequency from 100 kHz to 212.5 MHz (CMOS limit) without external components. Its dual-frequency selection is controlled via the FS pin, enabling hardware-switched clock domains without reconfiguration overhead.

It integrates an on-chip LDO regulator for supply noise rejection (3.0–3.5 ps jitter increase under 100 kHz–1 MHz VDD noise), supports active-high OE with internal pull-up, and features runt suppression on both power-on and OE assertion-ensuring glitch-free clock startup and clean output disable.

Key Specifications

Pinout & Package

Package: 2.5 × 3.2 mm, 6-pin surface-mount ceramic package (RoHS-compliant, Pb-free).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-frequency oscillator applications.

Compared with Si512BBA000104BAG, 512BBA000233BAG offers application-matched frequencies for datacom/FPGA use, while AK2-100.000MHZ-EV lacks dual-frequency capability entirely-making 512BBA000233BAG the only drop-in solution for hardware-switched 100/125 MHz clock trees.

Availability

512BBA000233BAG is available at Aetrix Electronics and suitable for FPGA/ASIC clock generation, Gigabit Ethernet PHY timing, and telecom line card synchronization requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.

Supply support for 512BBA000233BAG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of oscillator innovation.

The Si512/513 family was designed to replace multiple discrete XOs with a single programmable dual-frequency device-targeting high-reliability, low-jitter clocking in datacenter, telecom, and industrial systems where board space and supply chain simplification are critical.

FAQ

What are the exact output frequencies programmed into the 512BBA000233BAG?

The 512BBA000233BAG is factory-configured for two precise frequencies: 100.000 MHz (selected when FS = 0) and 125.000 MHz (selected when FS = 1). These values are permanently programmed into the device and cannot be modified in-system. Both frequencies meet ±50 ppm total stability over –40 °C to +85 °C and include 10-year aging.

Does the 512BBA000233BAG support LVDS or LVPECL output formats?

No, the 512BBA000233BAG is a CMOS-output variant (indicated by "C" in the third option code of its part number). It delivers single-ended CMOS logic levels (0.15×VDD to 0.85×VDD) and is not compatible with LVDS or LVPECL signaling. For differential outputs, Skyworks offers variants like 512BBA000104BAG with LVPECL/LVDS options-but those require different pinouts and termination.

How does the FS pin function, and what voltage levels are valid?

The FS pin on the 512BBA000233BAG is a logic input with internal 45 kΩ pull-down resistor. A logic low (≤0.20×VDD ≈ 0.66 V) selects the first frequency (100 MHz); a logic high (≥0.80×VDD ≈ 2.64 V) selects the second (125 MHz). The pin accepts standard 3.3 V CMOS levels and exhibits no metastability-switching occurs synchronously with the next clock edge after FS transition.

Is the 512BBA000233BAG pin-compatible with other Si512/513 variants in the same package size?

Yes-the 2.5×3.2 mm 6-pin package uses identical mechanical footprint and pin assignments across all Si512/513 variants, including CMOS and differential versions. However, pin functions differ: for example, Si512 LVDS variants use pins 4 and 5 as CLK+/CLK−, while the 512BBA000233BAG uses pin 4 as single-ended CLK and pin 5 as NC. PCB layout must match the specific variant's pinout.

What is the startup behavior of the 512BBA000233BAG after power application?

Upon VDD ramp-up, the 512BBA000233BAG achieves stable output within ≤10 ms (startup time TSU), with runt suppression ensuring no sub-cycle pulses appear on CLK. Output remains disabled until OE is asserted high, and frequency selection is determined by the FS pin state at power-on-no reset sequence or initialization delay is required.