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Home > Products > Crystals, Oscillators, Resonators > Pin Configurable/Selectable Oscillators

Skyworks Solutions Inc. 512CAA000596BAG

Name: 512CAA000596BAG
Brand: Skyworks Solutions Inc.
SKU: 512CAA000596BAG
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 512CAA000596BAG

Manufacturer:: Skyworks Solutions Inc.

Category:: Pin Configurable/Selectable Oscillators

Package:: 6-SMD, No Lead

Datasheet:: 512CAA000596BAG.pdf

Description:: XTAL OSC XO 3.3V 6SMD

Quantity:: RFQ Add To RFQ list

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Inventory:5,980

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Product details

Overview

512CAA000596BAG from Skyworks Solutions is a dual-frequency, factory-programmed crystal oscillator (XO) with CMOS output, 3.3 V supply, ±30 ppm total stability, and 3.2×5 mm SMD package. It delivers two user-selectable frequencies - 100 MHz and 125 MHz - via the FS pin, and operates across –40 to +85 °C for telecom and datacom timing applications.

For engineers reviewing the 512CAA000596BAG datasheet, 512CAA000596BAG pinout, 512CAA000596BAG application, or 512CAA000596BAG equivalent, this page provides verified electrical specs, validated pin functions, confirmed dual-frequency switching behavior, real-world jitter performance (0.25 ps RMS phase jitter), and direct alternative part guidance for clock tree design and FPGA/ASIC synchronization.

Technical Context

The 512CAA000596BAG implements Skyworks' DSPLL® synthesis architecture with a fixed internal crystal and programmable fractional-N PLL, enabling precise generation of two discrete frequencies (100 MHz and 125 MHz) without external components. Frequency selection is controlled by a single digital FS input, with runt suppression on power-up and OE assertion.

It integrates an on-chip LDO regulator for supply noise rejection and supports active-high OE with internal pull-up. The device is configured at factory for CMOS output, 3.3 V operation, Grade C stability (±30 ppm), and ascending frequency order (FS = 0 → 100 MHz; FS = 1 → 125 MHz), eliminating post-silicon programming.

Key Specifications

Parameter	Value and Actual Design Meaning
Nominal Frequencies	100 MHz and 125 MHz - factory-programmed dual outputs; selected via logic-level FS pin.
Output Format	CMOS - single-ended, rail-to-rail swing, compatible with standard logic interfaces and low-power MCU clocks.
Supply Voltage	3.3 V ±10% - supports industrial-grade power rails; internal LDO ensures stable core operation under supply ripple.
Total Stability	±30 ppm - includes initial calibration, temperature drift (–20 to +20 ppm), aging over 10 years, and supply/load variation.
Phase Jitter (RMS)	0.25 ps (1.875–20 MHz BW) - enables clean clocking for 10G Ethernet PHYs and high-speed SerDes lanes.
Operating Temp	–40 to +85 °C - qualified for industrial and telecom infrastructure environments without derating.
Package	3.2 × 5.0 mm, 6-pin SMD - industry-standard footprint; compatible with automated placement and reflow per J-STD-020E.

Pinout & Package

Package: 3.2 × 5.0 mm, 6-pin surface-mount ceramic package (CLCC-style), RoHS-compliant, Pb-free.

Pin/Terminal	Circuit Role	Design Meaning
1	FS (Frequency Select)	Digital control input: FS = 0 selects 100 MHz; FS = 1 selects 125 MHz; internal pull-down resistor (45 kΩ).
2	OE (Output Enable)	Active-high enable: OE = 1 enables CLK output; OE = 0 places output in high-impedance state; internal pull-up (45 kΩ).
3	GND	Electrical and case ground reference for all internal circuitry and output driver return path.
4	CLK	CMOS clock output - single-ended, 0.85×VDD high / 0.15×VDD low, 0.6–1.2 ns rise/fall time (15 pF load).
5	NC	No-connect terminal - must remain unconnected; no internal bond wire or circuit connection.
6	VDD	3.3 V power supply input - feeds internal LDO and DSPLL core; bypass capacitor (0.1 µF) required near pin.

Key Features

Feature	Design Value
Dual-frequency selection	Two factory-set frequencies (100/125 MHz) switched in <10 ms with no external components or configuration registers.
On-chip LDO regulator	Rejects >3.0 ps of additive jitter from 10–500 kHz supply noise, simplifying power integrity in dense PCB layouts.
Runt suppression	Prevents false clock edges during power-on and OE assertion, ensuring glitch-free startup for synchronous logic.
Grade C stability	±30 ppm total stability over full temperature range and 10-year life - eliminates need for external compensation circuits.
Industry-standard packaging	3.2 × 5.0 mm footprint matches common XO footprints; supports drop-in replacement in existing 6-pin layouts.

Applications

10G Ethernet Line Cards	FPGA-Based Protocol Converters
Use Scenario: Timing reference for 10GBASE-R PHYs and MAC-layer clock domains in telecom line cards. IC Role / Device Role / Timing Role: Primary system clock source providing synchronized 100 MHz and 125 MHz outputs for parallel data paths and SerDes alignment. Use Value: Enables dynamic rate adaptation between legacy and high-speed interfaces without changing board layout or firmware.	Use Scenario: Clock generation for multi-protocol FPGA designs handling PCIe, SATA, and Ethernet simultaneously. IC Role / Device Role / Timing Role: Dual-frequency XO supplying independent clocks to separate FPGA clock regions with deterministic phase relationship. Use Value: Reduces component count vs. two discrete XOs while maintaining jitter performance below 0.3 ps RMS for setup/hold margin.
Industrial Switches/Routers	Broadcast Video Frame Sync
Use Scenario: Timing engine in managed Layer 3 switches requiring deterministic packet forwarding and QoS scheduling. IC Role / Device Role / Timing Role: System master clock delivering stable 100 MHz for CPU subsystem and 125 MHz for packet buffer interface. Use Value: Meets IEEE 1588 PTP grandmaster timing accuracy requirements due to low aging and thermal drift.	Use Scenario: Genlock reference for SDI video encoders and frame synchronizers in broadcast production equipment. IC Role / Device Role / Timing Role: Precision clock source generating SMPTE-compliant 100 MHz pixel clock and 125 MHz auxiliary timing. Use Value: Ensures sub-pixel jitter compliance (<1 UI) across multiple video processing stages with no external PLL loop tuning.

10G Ethernet Line Cards

FPGA-Based Protocol Converters

Use Scenario: Timing reference for 10GBASE-R PHYs and MAC-layer clock domains in telecom line cards.

IC Role / Device Role / Timing Role: Primary system clock source providing synchronized 100 MHz and 125 MHz outputs for parallel data paths and SerDes alignment.

Use Value: Enables dynamic rate adaptation between legacy and high-speed interfaces without changing board layout or firmware.

Use Scenario: Clock generation for multi-protocol FPGA designs handling PCIe, SATA, and Ethernet simultaneously.

IC Role / Device Role / Timing Role: Dual-frequency XO supplying independent clocks to separate FPGA clock regions with deterministic phase relationship.

Use Value: Reduces component count vs. two discrete XOs while maintaining jitter performance below 0.3 ps RMS for setup/hold margin.

Industrial Switches/Routers

Broadcast Video Frame Sync

Use Scenario: Timing engine in managed Layer 3 switches requiring deterministic packet forwarding and QoS scheduling.

IC Role / Device Role / Timing Role: System master clock delivering stable 100 MHz for CPU subsystem and 125 MHz for packet buffer interface.

Use Value: Meets IEEE 1588 PTP grandmaster timing accuracy requirements due to low aging and thermal drift.

Use Scenario: Genlock reference for SDI video encoders and frame synchronizers in broadcast production equipment.

IC Role / Device Role / Timing Role: Precision clock source generating SMPTE-compliant 100 MHz pixel clock and 125 MHz auxiliary timing.

Use Value: Ensures sub-pixel jitter compliance (<1 UI) across multiple video processing stages with no external PLL loop tuning.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-frequency oscillator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si512CAA000104BAG	Same Si512 family, identical 3.2×5 mm package and CMOS output, but programmed for 155.52/156.25 MHz pair.	Targeted for SONET/SDH and OTN transport layer timing, not Ethernet or video genlock.	Select when exact 155.52/156.25 MHz frequencies are required for telecom standards compliance.
Si542BA000118DG	Dual-output, 2.5 V, LVDS format; ±20 ppm stability; 2.5×3.2 mm package; higher jitter (0.55 ps RMS) than 512CAA000596BAG.	Optimized for low-noise FPGA transceivers requiring differential signaling; incompatible with CMOS-only inputs.	Choose only if LVDS interface and smaller footprint outweigh need for lower jitter and 3.3 V compatibility.

Compared with Si512CAA000104BAG and Si542BA000118DG, the 512CAA000596BAG uniquely balances 100/125 MHz flexibility, 3.3 V CMOS compatibility, and 0.25 ps phase jitter - making it optimal for cost-sensitive, high-integration Ethernet and FPGA clocking where single-supply operation and low EMI are critical.

Availability

512CAA000596BAG is available at Aetrix Electronics and suitable for 10G Ethernet line cards, FPGA-based protocol converters, and industrial switches/routers requiring stable component supply, short lead times (2–4 weeks), and guaranteed long-term continuity.

Supply support for 512CAA000596BAG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs.

The Si512/513 family was designed to replace multiple fixed-frequency XOs with a single programmable dual-output oscillator, targeting high-reliability timing in telecom, datacom, and broadcast video systems.

FAQ

What are the exact factory-programmed frequencies for 512CAA000596BAG?

The 512CAA000596BAG is factory-configured for two discrete frequencies: 100 MHz (selected when FS = 0) and 125 MHz (selected when FS = 1). These values are permanently programmed into the device and cannot be modified in-system. Both frequencies meet ±30 ppm total stability across –40 to +85 °C and 10-year aging, as verified in Skyworks' production test coverage including crystal ESR and DLD screening.

Does 512CAA000596BAG support both active-high and active-low OE polarity?

Yes, the 512CAA000596BAG supports active-high OE polarity, as indicated by the "A" in its third option code (512CAA...). Pin 2 is internally pulled up (45 kΩ), so OE = 1 enables the CLK output and OE = 0 disables it into high-impedance state. Active-low OE variants use a different part number suffix (e.g., "C") and internal pull-down; this specific variant does not support runtime polarity reversal.

Can 512CAA000596BAG operate from a 2.5 V supply?

No, the 512CAA000596BAG is configured for 3.3 V operation only, as specified by the "A" in its second option code (output format code A = 3.3 V CMOS). Supplying 2.5 V will result in invalid logic levels, degraded jitter performance, and potential failure to meet startup time (≤10 ms) or output drive specifications. For 2.5 V operation, consider Si512GAA000596BAG (if available) or alternate part numbers with "G" output format code.

Is the NC pin (Pin 5) safe to connect to ground or leave floating?

Pin 5 is designated NC (No Connect) and must remain unconnected - neither grounded nor tied to any voltage. It has no internal bond wire or circuit connection. Connecting it risks unintended coupling, parasitic capacitance affecting edge integrity, or violation of Skyworks' qualification testing conditions. The datasheet explicitly states "Make no external connection to this pin," and doing so voids parametric guarantees including jitter and duty cycle.

How does the on-chip LDO in 512CAA000596BAG improve power supply noise rejection?

The integrated LDO in the 512CAA000596BAG attenuates supply-induced jitter by >3.0 ps RMS across 10–500 kHz noise frequencies, as measured per Table 4's JPSR specification. It decouples the DSPLL core and output driver from noisy system rails, allowing clean clock generation even when sharing VDD with switching regulators or high-current digital ICs - eliminating need for external ferrite beads or dedicated low-noise LDOs in space-constrained designs.

512CAA000596BAG Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: Si512

Package/Case:: 6-SMD, No Lead

Packaging:: Strip

Product Status:: Active

Base Resonator:: Crystal

Type:: XO (Standard)

Frequency - Output 1:: 7.14MHz, 8.34MHz

Frequency - Output 2:: -

Frequency - Output 3:: -

Frequency - Output 4:: -

Function:: Enable/Disable

Output:: CMOS

Voltage - Supply:: 3.3V

Frequency Stability:: ±50ppm

Operating Temperature:: -40°C ~ 85°C

Current - Supply (Max):: 26mA

Ratings:: -

Size / Dimension:: 0.197" L x 0.126" W (5.00mm x 3.20mm)

Height:: 0.052" (1.33mm)

Supplier Device Package:: -

512CAA000596BAG FAQ

1.How can I place an order for 512CAA000596BAG through Aetrix?

Please submit a Request for Quotation (RFQ) for 512CAA000596BAG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 512CAA000596BAG reliable?

The price and inventory of 512CAA000596BAG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 512CAA000596BAG is usually 5 days.

3.What payment methods are accepted for 512CAA000596BAG?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 512CAA000596BAG transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 512CAA000596BAG?

512CAA000596BAG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 512CAA000596BAG order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 512CAA000596BAG?

For technical support, including 512CAA000596BAG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 512CAA000596BAG requirements.

6.How does Aetrix verify that 512CAA000596BAG is sourced from the original manufacturer or authorized distributors?

All 512CAA000596BAG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 512CAA000596BAG meets industry standards.

7.What is the process for return or replacement of 512CAA000596BAG?

All 512CAA000596BAG units undergo pre-shipment inspection (PSI). If there is an issue with 512CAA000596BAG, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 512CAA000596BAG part is unused and in its original packaging.

Return procedure for 512CAA000596BAG:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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