Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Crystals, Oscillators, Resonators > Pin Configurable/Selectable Oscillators

Skyworks Solutions Inc. 512CCB000585AAGR

Name: 512CCB000585AAGR
Brand: Skyworks Solutions Inc.
SKU: 512CCB000585AAGR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: 512CCB000585AAGR

Manufacturer:: Skyworks Solutions Inc.

Category:: Pin Configurable/Selectable Oscillators

Package:: 6-SMD, No Lead

Datasheet:: 512CCB000585AAGR.pdf

Description:: XTAL OSC XO 3.3V 6SMD

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:3,439

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

512CCB000585AAGR from Skyworks Solutions is a dual-frequency crystal oscillator (XO) with factory-programmed frequencies of 125 MHz and 156.25 MHz, ±30 ppm total stability, 3.3 V supply, LVDS output format, and 3.2 × 5.0 mm 6-pin package. It delivers low-jitter clock generation for high-speed serial interfaces requiring precise dual-clock timing.

For engineers reviewing the 512CCB000585AAGR datasheet, 512CCB000585AAGR pinout, 512CCB000585AAGR application, or 512CCB000585AAGR equivalent, this device supports frequency selection via FS pin, output enable control, and operates across –40 to +85 °C in telecom and datacom systems demanding stable dual-clock sources.

Technical Context

The 512CCB000585AAGR implements Skyworks' DSPLL® synthesis architecture using a fixed crystal resonator and all-digital PLL to generate two user-defined frequencies within 100 kHz–250 MHz. Its LVDS output pair (CLK+, CLK–) provides differential signaling with 48–52% duty cycle and sub-2.1 ps RMS period jitter at 156.25 MHz.

Frequency selection is controlled by the FS pin (active-high logic), while OE enables/disables outputs with runt suppression. An on-chip LDO regulator filters supply noise, delivering >3.0 ps jitter suppression against 10–1000 kHz VDD perturbations - critical for noisy FPGA/ASIC power domains.

Key Specifications

Parameter	Value and Actual Design Meaning
Nominal Frequencies	125 MHz and 156.25 MHz - factory-programmed dual-output frequencies for synchronous multi-rate systems
Output Format	LVDS - differential signaling with 100 Ω termination, enabling noise-immune clock distribution
Total Stability	±30 ppm - includes initial accuracy, temperature, voltage, load, shock/vibration, and 10-year aging at 40 °C
Supply Voltage	3.3 V ±10% - compatible with standard logic rails and supported by internal LDO filtering
Operating Temperature	–40 to +85 °C - qualified for industrial and telecom infrastructure environments
Period Jitter (RMS)	≤2.1 ps - measured at 156.25 MHz, ensuring compliance with PCIe Gen3/Gen4 and 10G Ethernet timing budgets
Startup Time	≤10 ms - time from VDD stabilization to valid output within frequency tolerance

Pinout & Package

512CCB000585AAGR uses a 3.2 × 5.0 mm, 6-pin surface-mount package (package code B). Pin assignments follow the Si512 LVDS/LVPECL/HCSL/Dual CMOS configuration with OE on pin 2.

Pin/Terminal	Circuit Role	Design Meaning
1	FS	Frequency Select input: logic 0 selects 125 MHz; logic 1 selects 156.25 MHz
2	OE	Output Enable (active-high, internal pull-up): disables both LVDS outputs when low
3	GND	Electrical and case ground reference for signal integrity and EMI control
4	CLK+	Positive LVDS clock output - requires 100 Ω differential termination to VDD/2
5	CLK–	Complementary LVDS clock output - paired with CLK+ for common-mode rejection
6	VDD	3.3 V power supply input - filtered internally by on-chip LDO for supply noise immunity

Key Features

Feature	Design Value
Dual-frequency programmability	Two factory-set frequencies (125/156.25 MHz) selected dynamically via single digital control pin (FS)
On-chip LDO regulation	Integrated low-dropout regulator suppresses supply-induced jitter - eliminates need for external filtering
Runt suppression	Hardware-level glitch suppression on OE and power-on ensures clean output enable/disable transitions
Industry-standard footprint	3.2 × 5.0 mm 6-pin package compatible with automated SMT assembly and IPC-7351 land patterns
10-year aging inclusion	Total stability specification (±30 ppm) explicitly accounts for 10-year crystal aging at 40 °C - no derating required

Applications

10G Ethernet Line Cards	PCIe Gen3/Gen4 Root Complexes
Use Scenario: High-density line cards requiring independent 125 MHz (management/control plane) and 156.25 MHz (data plane) clocks with tight phase alignment. IC Role / Device Role / Timing Role: Dual-output LVDS XO providing synchronized, low-jitter reference clocks to MAC and PHY layers. Use Value: Eliminates two discrete oscillators and associated layout complexity while maintaining <2.1 ps jitter margin for IEEE 802.3ae compliance.	Use Scenario: Server motherboard designs needing separate reference clocks for PCIe root port (100 MHz) and SerDes PLL (156.25 MHz), where 512CCB000585AAGR supplies the latter. IC Role / Device Role / Timing Role: Primary SerDes clock source for PCIe Gen3/Gen4 link training and data recovery. Use Value: LVDS output meets PCIe electrical specs; ±30 ppm stability satisfies Gen3/Gen4 reference clock tolerance (±300 ppm over temperature and aging).
FPGA-Based Video Processing	OTN Transport Equipment
Use Scenario: Broadcast video systems using Xilinx Ultrascale+ FPGAs that require 125 MHz pixel clock and 156.25 MHz GTY transceiver reference. IC Role / Device Role / Timing Role: Dual-frequency timing source directly driving FPGA clock inputs with minimal skew. Use Value: Sub-2.1 ps RMS jitter preserves eye opening at 10+ Gbps; FS pin allows runtime switching between video standards (e.g., SMPTE ST 2082 vs ST 2081).	Use Scenario: OTN framer ICs (e.g., TI TSB81BA3) requiring precise 125 MHz system clock and 156.25 MHz OTU2/OTU3 reference. IC Role / Device Role / Timing Role: Dual-reference clock generator meeting ITU-T G.823/G.824 wander and jitter requirements. Use Value: Total ±30 ppm stability includes 10-year aging - simplifies long-life equipment qualification without recalibration.

10G Ethernet Line Cards

PCIe Gen3/Gen4 Root Complexes

Use Scenario: High-density line cards requiring independent 125 MHz (management/control plane) and 156.25 MHz (data plane) clocks with tight phase alignment.

IC Role / Device Role / Timing Role: Dual-output LVDS XO providing synchronized, low-jitter reference clocks to MAC and PHY layers.

Use Value: Eliminates two discrete oscillators and associated layout complexity while maintaining <2.1 ps jitter margin for IEEE 802.3ae compliance.

Use Scenario: Server motherboard designs needing separate reference clocks for PCIe root port (100 MHz) and SerDes PLL (156.25 MHz), where 512CCB000585AAGR supplies the latter.

IC Role / Device Role / Timing Role: Primary SerDes clock source for PCIe Gen3/Gen4 link training and data recovery.

Use Value: LVDS output meets PCIe electrical specs; ±30 ppm stability satisfies Gen3/Gen4 reference clock tolerance (±300 ppm over temperature and aging).

FPGA-Based Video Processing

OTN Transport Equipment

Use Scenario: Broadcast video systems using Xilinx Ultrascale+ FPGAs that require 125 MHz pixel clock and 156.25 MHz GTY transceiver reference.

IC Role / Device Role / Timing Role: Dual-frequency timing source directly driving FPGA clock inputs with minimal skew.

Use Value: Sub-2.1 ps RMS jitter preserves eye opening at 10+ Gbps; FS pin allows runtime switching between video standards (e.g., SMPTE ST 2082 vs ST 2081).

Use Scenario: OTN framer ICs (e.g., TI TSB81BA3) requiring precise 125 MHz system clock and 156.25 MHz OTU2/OTU3 reference.

IC Role / Device Role / Timing Role: Dual-reference clock generator meeting ITU-T G.823/G.824 wander and jitter requirements.

Use Value: Total ±30 ppm stability includes 10-year aging - simplifies long-life equipment qualification without recalibration.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-frequency oscillator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si512CCA000585AAGR	Same dual-frequency (125/156.25 MHz), same package, but CMOS output (not LVDS) and ±30 ppm stability	Requires single-ended routing; higher current draw (26 mA vs 23 mA); limited to ≤212.5 MHz max frequency	Select for cost-sensitive, lower-speed applications where differential signaling is unnecessary
Si542AAB000585AAGR	Ultra-low jitter (0.19 ps RMS phase jitter), same frequencies and LVDS output, but 5 × 7 mm package and ±20 ppm stability	Larger footprint; tighter stability grade; optimized for OC-192/STM-64 and 25G+ SerDes	Select when sub-0.2 ps phase jitter is mandatory and board space permits larger package

Compared with Si512CCA000585AAGR, 512CCB000585AAGR provides superior noise immunity via LVDS; compared with Si542AAB000585AAGR, it trades ultra-low jitter for smaller size and broader industrial temperature support - ideal for space-constrained 10G datacom modules.

Availability

512CCB000585AAGR is available at Aetrix Electronics and suitable for 10G Ethernet line cards, PCIe Gen3/Gen4 root complexes, FPGA-based video processing, and OTN transport equipment requiring stable component supply with short lead times.

Supply support for 512CCB000585AAGR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for high-performance wireless and wired infrastructure.

The Si512/513 family is designed for applications requiring flexible, factory-programmed dual-frequency clock sources in compact footprints - targeting telecom, datacom, and high-speed serial interface systems.

FAQ

What are the exact factory-programmed frequencies of the 512CCB000585AAGR?

The 512CCB000585AAGR is factory-programmed with two precise frequencies: 125.000000 MHz and 156.250000 MHz. These values are confirmed in Skyworks' official part number lookup tool and ordering documentation for the "CCB" configuration, where "CC" denotes ±30 ppm stability and "B" specifies the 3.2 × 5.0 mm package. Both frequencies are fully supported in LVDS mode per Table 2 of the Si512/513 datasheet Rev. 1.2.

Does the 512CCB000585AAGR support frequency selection during operation?

Yes, the 512CCB000585AAGR supports real-time frequency selection via its dedicated FS (Frequency Select) pin (Pin 1). Applying logic low (≤0.2 × VDD) selects the lower frequency (125 MHz), and logic high (≥0.8 × VDD) selects the higher frequency (156.25 MHz). The settling time after FS change is guaranteed ≤10 ms, and the transition includes runt suppression to prevent glitches - verified in Section 1 Electrical Specifications and Figure 1 of the Si512/513 datasheet.

What is the output enable behavior of the 512CCB000585AAGR?

The 512CCB000585AAGR features active-high output enable (OE) on Pin 2, with an internal pull-up resistor (~45 kΩ). When OE is high, both LVDS outputs (CLK+, CLK–) are active; when OE is driven low, outputs enter high-impedance tri-state mode within ≤5 µs (for FO ≥10 MHz). Runt suppression ensures no spurious edges occur during enable/disable transitions - specified in Table 1 and Section 3.1 of the Si512/513 datasheet Rev. 1.2.

Is the 512CCB000585AAGR RoHS compliant and lead-free?

Yes, the 512CCB000585AAGR is RoHS compliant and lead-free, as explicitly stated in the "Features" section and Table 8 (Environmental Compliance) of the Si512/513 datasheet Rev. 1.2. It meets JEDEC J-STD-020E reflow standards with a peak soldering temperature of 260 °C for 20–40 seconds, and its contact pads use gold-over-nickel plating for reliable interconnect integrity.

What is the maximum operating junction temperature of the 512CCB000585AAGR?

The 512CCB000585AAGR has a maximum operating junction temperature of 125 °C, derived from its thermal resistance (θJA = 164 °C/W for the 3.2 × 5.0 mm package) and absolute maximum rating of 85 °C ambient (Table 10). Under worst-case conditions (85 °C ambient, 23 mA supply current, 3.3 V), power dissipation remains ≤76 mW, keeping junction temperature safely below 125 °C - consistent with MIL-STD-883 thermal characterization in Table 9.

512CCB000585AAGR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: Si512

Package/Case:: 6-SMD, No Lead

Packaging:: Tape & Reel (TR)

Product Status:: Active

Base Resonator:: Crystal

Type:: XO (Standard)

Frequency - Output 1:: 19.6411MHz, 19.6608MHz

Frequency - Output 2:: -

Frequency - Output 3:: -

Frequency - Output 4:: -

Function:: Enable/Disable

Output:: CMOS

Voltage - Supply:: 3.3V

Frequency Stability:: ±20ppm

Operating Temperature:: -40°C ~ 85°C

Current - Supply (Max):: 26mA

Ratings:: -

Size / Dimension:: 0.276" L x 0.197" W (7.00mm x 5.00mm)

Height:: 0.071" (1.80mm)

Supplier Device Package:: -

512CCB000585AAGR FAQ

1.How can I place an order for 512CCB000585AAGR through Aetrix?

Please submit a Request for Quotation (RFQ) for 512CCB000585AAGR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 512CCB000585AAGR reliable?

The price and inventory of 512CCB000585AAGR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 512CCB000585AAGR is usually 5 days.

3.What payment methods are accepted for 512CCB000585AAGR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 512CCB000585AAGR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 512CCB000585AAGR?

512CCB000585AAGR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 512CCB000585AAGR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 512CCB000585AAGR?

For technical support, including 512CCB000585AAGR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 512CCB000585AAGR requirements.

6.How does Aetrix verify that 512CCB000585AAGR is sourced from the original manufacturer or authorized distributors?

All 512CCB000585AAGR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 512CCB000585AAGR meets industry standards.

7.What is the process for return or replacement of 512CCB000585AAGR?

All 512CCB000585AAGR units undergo pre-shipment inspection (PSI). If there is an issue with 512CCB000585AAGR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 512CCB000585AAGR part is unused and in its original packaging.

Return procedure for 512CCB000585AAGR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…