My Inquiry
My Account
Skyworks Solutions Inc. 512FBA000132AAG
- Part No.:
- 512FBA000132AAG
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Pin Configurable/Selectable Oscillators
- Package:
- 6-SMD, No Lead
- Datasheet:
-
512FBA000132AAG.pdf
- Description:
- XTAL OSC XO 2.5V 6SMD
- Quantity:
- Payment:
- Shipping:
Inventory:2,443
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
512FBA000132AAG from Skyworks Solutions is a dual-frequency crystal oscillator (XO) with factory-programmed frequencies of 100 MHz and 132.8125 MHz, operating at 3.3 V supply, ±30 ppm total stability (Grade C), LVPECL output format, and housed in a 3.2 × 5.0 mm 6-pin surface-mount package. It delivers low-jitter clocking for high-speed serial interfaces requiring precise dual-clock switching.
For engineers reviewing the 512FBA000132AAG datasheet, 512FBA000132AAG pinout, 512FBA000132AAG application, or 512FBA000132AAG equivalent, key selection criteria include dual-frequency switching via FS pin, LVPECL output drive capability, 1.3 ps RMS period jitter at 156.25 MHz, and compatibility with PCIe Gen3/Gen4 reference clock requirements.
Technical Context
The 512FBA000132AAG implements Skyworks' DSPLL® synthesis architecture using a fixed internal crystal and programmable fractional-N PLL to generate two user-defined frequencies across 100 kHz–250 MHz. Frequency selection is controlled by the logic state of the FS pin, enabling seamless switching between 100 MHz and 132.8125 MHz without external components.
It integrates an on-chip LDO regulator for supply noise rejection, supports active-high OE control with internal pull-up, and features runt suppression on both OE and power-on transitions. The device operates over –40 °C to +85 °C and meets MIL-STD-883 mechanical reliability standards.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Nominal Frequencies | 100.000000 MHz and 132.812500 MHz - factory-programmed dual-output points for protocol-matched clock sourcing |
| Output Format | LVPECL - differential signaling with 0.8 VPPSE swing into 50 Ω, suitable for high-speed backplane and SerDes applications |
| Total Stability | ±30 ppm - includes initial accuracy, temperature, voltage, load, shock/vibration, and 10-year aging at 40 °C |
| Supply Voltage | 3.3 V ±10% - compatible with standard logic rails; internal LDO filters supply noise to maintain jitter performance |
| Period Jitter (RMS) | 1.3 ps - measured at 156.25 MHz per JEDEC JESD65B; ensures compliance with PCIe Gen3/Gen4 and 10G Ethernet jitter budgets |
| Startup Time | ≤10 ms - time from VDD reaching minimum to output frequency within specification; enables fast system boot |
| Operating Temperature | –40 °C to +85 °C - industrial-grade thermal range for embedded telecom and networking equipment |
Pinout & Package
512FBA000132AAG uses the Si512 LVPECL/LVDS/HCSL/Dual CMOS pinout configuration in a 3.2 × 5.0 mm 6-pin CLCC package (package code B). Pin 1 = FS, Pin 2 = OE, Pin 3 = GND, Pin 4 = CLK+, Pin 5 = CLK–, Pin 6 = VDD.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (FS) | Frequency Select input | Logic level selects between f₀ = 100 MHz (FS = 0) and f₁ = 132.8125 MHz (FS = 1); TTL-compatible with internal bias |
| 2 (OE) | Output Enable input | Active-high enable with internal pull-up; disables outputs to high-impedance when low, reducing system power during idle |
| 3 (GND) | Electrical ground | Common reference for all signals and power; requires low-inductance PCB connection to minimize noise coupling |
| 4 (CLK+) | Differential clock output | LVPECL positive output; must be terminated to VDD – 2 V with 50 Ω for proper signal integrity and jitter performance |
| 5 (CLK–) | Differential clock output | LVPECL complementary output; paired with CLK+ to deliver 180° phase relationship and common-mode noise rejection |
| 6 (VDD) | Power supply input | 3.3 V ±10% supply; filtered internally by on-chip LDO to suppress supply-induced jitter up to 1 MHz |
Key Features
| Feature | Design Value |
|---|---|
| Dual-frequency programmability | Two factory-set frequencies (100 MHz / 132.8125 MHz) selectable via single digital control line - eliminates need for multiple oscillators or external multiplexers |
| On-chip LDO regulation | Integrated low-dropout regulator rejects >3 ps of additive jitter from 10 kHz–1 MHz supply noise - simplifies power delivery design in noisy SoC environments |
| Runt suppression | Hardware-level filtering on OE and power-on edges prevents false clock edges during assertion/deassertion - avoids metastability in downstream logic |
| Industry-standard footprint | 3.2 × 5.0 mm 6-pin CLCC package - drop-in compatible with existing layout footprints for Si512/Si513 family and legacy XO replacements |
| 10-year aging inclusion | Total stability spec (±30 ppm) explicitly includes 10-year aging at 40 °C - enables long-lifecycle product qualification without derating |
Applications
| PCI Express Reference Clock | Gigabit Ethernet PHY Timing |
|---|---|
Use Scenario: Providing primary reference clocks to PCIe Gen3 root complex and endpoint devices requiring dual-frequency support for link training and spread-spectrum modes. IC Role / Device Role / Timing Role: Dual-output LVPECL XO delivering 100 MHz (for LTSSM) and 132.8125 MHz (for Gen3 reference) with sub-1.5 ps RMS jitter. Use Value: Eliminates need for separate oscillators or clock generators, reduces BOM count, and guarantees timing margin compliance per PCI-SIG ECN requirements. | Use Scenario: Synchronizing 10GBASE-R and 10GBASE-KR PHY layers in switches and NICs where dual-rate clocking improves link negotiation robustness. IC Role / Device Role / Timing Role: Factory-configured dual-frequency source switching between 100 MHz (for MAC interface) and 132.8125 MHz (for 10G serial lane). Use Value: Enables single-device support for both legacy and high-speed Ethernet modes without layout changes or firmware updates. |
| Telecom Line Card Timing | FPGA-Based Protocol Converter |
Use Scenario: Generating synchronized clocks for multi-port TDM-to-packet gateways in access and aggregation nodes requiring stable dual-rate timing. IC Role / Device Role / Timing Role: Industrial-grade (–40 °C to +85 °C) dual-frequency XO with ±30 ppm stability over full temperature and lifetime. Use Value: Meets Telcordia GR-1244-CORE long-term stability requirements while supporting dynamic rate switching via FPGA-controlled FS pin. | Use Scenario: Providing reconfigurable clock sources to Xilinx Versal or Intel Agilex FPGAs implementing multi-protocol bridging (e.g., USB 3.2 ↔ PCIe ↔ SATA). IC Role / Device Role / Timing Role: Low-jitter LVPECL oscillator with hardware-based frequency selection, decoupled from FPGA configuration bitstream. Use Value: Offloads clock management from FPGA logic, preserves I/O resources, and ensures deterministic startup timing independent of configuration sequence. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-frequency oscillator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si512FBA000104BAGR | Same Si512 family, 3.3 V LVPECL, ±30 ppm, but programmed for 155.52 MHz / 156.25 MHz - higher frequencies optimized for SONET/OTN and Fibre Channel | Targeted at telecom transport layer rather than PCIe/GbE; incompatible with 100 MHz system clock domains | Select only if application requires exact OC-3/OC-12 or 8G/16G FC reference frequencies. |
| Si542AAB000132AAG | Si54x series; single-output, not dual-frequency; same 132.8125 MHz frequency, ±20 ppm, lower jitter (0.9 ps RMS), but no FS pin or second frequency | Lacks hardware-based dual-frequency switching; requires external multiplexer or FPGA logic to emulate dual-clock behavior | Choose when only one frequency is needed and ultra-low jitter is prioritized over flexibility. |
Compared with Si512FBA000104BAGR and Si542AAB000132AAG, the 512FBA000132AAG uniquely balances PCIe-relevant dual-frequency pairing (100/132.8125 MHz), industrial temperature operation, and hardware-selectable switching - making it optimal for embedded systems needing deterministic, low-risk clock architecture without FPGA intervention.
Availability
512FBA000132AAG is available at Aetrix Electronics and suitable for PCIe Gen3/Gen4 reference clocking, 10GbE PHY synchronization, and telecom line card timing requiring stable component supply across extended production lifecycles.
Supply support for 512FBA000132AAG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.
The Si512/513 family was designed specifically for high-reliability, factory-programmable dual-frequency clock generation in space-constrained, noise-sensitive applications such as networking, data center, and telecom equipment.
FAQ
What are the exact factory-programmed frequencies of the 512FBA000132AAG?
The 512FBA000132AAG is factory-programmed for two precise frequencies: 100.000000 MHz (f₀) and 132.812500 MHz (f₁). These values are confirmed by Skyworks' part number decoding - "F" indicates 3.3 V LVPECL output, "B" denotes ±30 ppm stability grade, and "000132" maps to the 132.8125 MHz secondary frequency per Skyworks' frequency lookup database. The 512FBA000132AAG does not support field reprogramming.
Does the 512FBA000132AAG support both LVPECL and CMOS output formats?
No, the 512FBA000132AAG is configured exclusively for LVPECL output, as indicated by the "F" in its part number prefix per Skyworks' ordering convention. CMOS variants use different codes (e.g., "C", "G", "K"). Attempting to drive CMOS loads with the 512FBA000132AAG's LVPECL outputs will result in incorrect logic levels and potential damage due to voltage mismatch; proper termination to VDD – 2 V is mandatory.
How is frequency selection implemented on the 512FBA000132AAG?
Frequency selection on the 512FBA000132AAG is performed via the FS (Frequency Select) pin (Pin 1). When FS = 0 (logic low), the device outputs 100.000000 MHz; when FS = 1 (logic high), it outputs 132.812500 MHz. The pin accepts standard TTL logic levels and includes internal biasing - no external pull-up/down resistors are required. Switching occurs within 10 ms of FS transition.
What is the supply current draw of the 512FBA000132AAG under typical operating conditions?
The 512FBA000132AAG draws 39–43 mA typical supply current when enabled and operating at 3.3 V with LVPECL output, as specified in Table 1 of the Si512/513 datasheet. In tristate (output disabled), current drops to ≤18 mA. This value assumes 100 MHz or 132.8125 MHz operation into properly terminated 50 Ω loads; current increases slightly at higher frequencies within the 250 MHz limit.
Is the 512FBA000132AAG RoHS compliant and lead-free?
Yes, the 512FBA000132AAG is RoHS compliant and lead-free, as confirmed in the "Features" section and Table 8 of the official Skyworks Si512/513 datasheet (Rev. 1.2). It meets JEDEC J-STD-020E reflow standards with a peak soldering temperature of 260 °C and is supplied in tape-and-reel packaging (suffix "R" in part number).
512FBA000132AAG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- Si512
- Package/Case:
- 6-SMD, No Lead
- Packaging:
- Strip
- Product Status:
- Active
- Base Resonator:
- Crystal
- Type:
- XO (Standard)
- Frequency - Output 1:
- 148.35MHz, 148.5MHz
- Frequency - Output 2:
- -
- Frequency - Output 3:
- -
- Frequency - Output 4:
- -
- Function:
- Enable/Disable
- Output:
- LVDS
- Voltage - Supply:
- 2.5V
- Frequency Stability:
- ±25ppm
- Operating Temperature:
- -40°C ~ 85°C
- Current - Supply (Max):
- 23mA
- Ratings:
- -
- Size / Dimension:
- 0.276" L x 0.197" W (7.00mm x 5.00mm)
- Height:
- 0.071" (1.80mm)
- Supplier Device Package:
- -
512FBA000132AAG FAQ
1.How can I place an order for 512FBA000132AAG through Aetrix?
Please submit a Request for Quotation (RFQ) for 512FBA000132AAG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 512FBA000132AAG reliable?
The price and inventory of 512FBA000132AAG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 512FBA000132AAG is usually 5 days.
3.What payment methods are accepted for 512FBA000132AAG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 512FBA000132AAG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 512FBA000132AAG?
512FBA000132AAG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 512FBA000132AAG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 512FBA000132AAG?
For technical support, including 512FBA000132AAG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 512FBA000132AAG requirements.
6.How does Aetrix verify that 512FBA000132AAG is sourced from the original manufacturer or authorized distributors?
All 512FBA000132AAG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 512FBA000132AAG meets industry standards.
7.What is the process for return or replacement of 512FBA000132AAG?
All 512FBA000132AAG units undergo pre-shipment inspection (PSI). If there is an issue with 512FBA000132AAG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 512FBA000132AAG part is unused and in its original packaging.
Return procedure for 512FBA000132AAG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
512FBA000132AAG Tags
-
ASEMDHC-L-R
Abracon LLC
-
513FCA000270AAG
Skyworks Solutions Inc.
-
LMK61PD0A2-SIAT
Texas Instruments
-
ASEMDLV-LR
Abracon LLC
2x1,6x0,9.JPG)
-
AMPDAFI-A09T
Abracon LLC
3,2x2,5x0,9.JPG)
-
AMPDEFH-A04T
Abracon LLC
-
534DC000596DG
Skyworks Solutions Inc.
-
ASEMCLV
Abracon LLC
-
DSC6021CI2A-009TT
Microchip Technology
-
DSC6021CI2A-009UT
Microchip Technology
-
DSC6021CI2A-009WT
Microchip Technology
-
DSC6021CI2A-009YT
Microchip Technology
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
