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Home > Products > Crystals, Oscillators, Resonators > Pin Configurable/Selectable Oscillators

Skyworks Solutions Inc. 513ACA000594AAG

Name: 513ACA000594AAG
Brand: Skyworks Solutions Inc.
SKU: 513ACA000594AAG
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 513ACA000594AAG

Manufacturer:: Skyworks Solutions Inc.

Category:: Pin Configurable/Selectable Oscillators

Package:: 6-SMD, No Lead

Datasheet:: 513ACA000594AAG.pdf

Description:: XTAL OSC XO 3.3V 6SMD

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Inventory:6,451

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Product details

Overview

513ACA000594AAG from Skyworks Solutions is a dual-frequency crystal oscillator (XO) with factory-programmed frequencies of 100 MHz and 156.25 MHz, ±30 ppm total stability (Grade C), 3.3 V supply, LVPECL output format, and OE on pin 1 in a 3.2 × 5.0 mm 6-pin package. It delivers low-jitter clock generation for high-speed serial interfaces requiring precise dual-clock timing.

For engineers reviewing the 513ACA000594AAG datasheet, 513ACA000594AAG pinout, 513ACA000594AAG application, or 513ACA000594AAG equivalent, key selection criteria include dual-frequency switching via FS pin, LVPECL jitter performance (0.31 ps RMS phase jitter, 1.875–20 MHz), supply noise rejection (3.0–3.5 ps additive jitter), and industrial temperature range (–40 to +85 °C).

Technical Context

The 513ACA000594AAG implements Skyworks' DSPLL® synthesis architecture using a fixed crystal resonator and all-digital PLL to generate two user-specified frequencies across 100 kHz–250 MHz without external components. Its integrated LDO regulator filters supply noise, enabling stable operation in electrically noisy environments.

Frequency selection is controlled by the FS pin (active-high logic), while OE (also active-high, internal pull-up) enables/disables outputs with runt suppression. The device supports LVPECL differential signaling with 50 Ω termination to VDD – 2 V, delivering 0.55–0.90 VPPSE swing and 48–52% duty cycle.

Key Specifications

Parameter	Value and Actual Design Meaning
Nominal Frequencies	100 MHz and 156.25 MHz - factory-programmed dual outputs selectable via FS pin
Output Format	LVPECL - differential signaling with 50 Ω load to VDD – 2 V, enabling robust noise immunity in high-speed backplanes
Total Stability	±30 ppm - includes initial accuracy, temp, voltage, load, shock/vibration, and 10-year aging at 40 °C
Phase Jitter (RMS)	0.31 ps (1.875–20 MHz) - meets stringent requirements for PCIe Gen3/Gen4 and 10G Ethernet reference clocks
Supply Voltage	3.3 V ±10% - compatible with standard logic rails; internal LDO ensures clean core regulation
Operating Temp	–40 to +85 °C - qualified for industrial and telecom infrastructure applications
Package	3.2 × 5.0 mm, 6-pin - industry-standard footprint enabling drop-in replacement in space-constrained designs

Pinout & Package

Package: 3.2 × 5.0 mm, 6-pin surface-mount CLCC (RoHS-compliant, Pb-free). Pin 1 = OE (Output Enable, active-high, internal pull-up); Pin 2 = FS (Frequency Select, active-high); Pin 3 = GND; Pin 4 = CLK+; Pin 5 = CLK–; Pin 6 = VDD.

Pin/Terminal	Circuit Role	Design Meaning
1	OE	Active-high output enable with internal pull-up; disables both outputs when low, with runt suppression during power-on
2	FS	Active-high frequency select; selects 100 MHz when low, 156.25 MHz when high
3	GND	Electrical and case ground reference for all signals and power return path
4	CLK+	Differential LVPECL clock output (positive phase); requires 50 Ω termination to VDD – 2 V
5	CLK–	Differential LVPECL clock output (complementary phase); matched routing required for skew control
6	VDD	3.3 V ±10% main supply; powers internal LDO and output drivers; decoupling near pin essential

Key Features

Feature	Design Value
Dual-frequency programmability	Two factory-set frequencies (100/156.25 MHz) switchable in real time via single FS pin-eliminates need for multiple oscillators
DSPLL® synthesis	Fixed-crystal-based digital PLL architecture improves reliability vs. traditional XOs and enables wide-frequency flexibility without custom crystals
Integrated LDO regulator	On-chip LDO filters supply noise, reducing additive jitter to ≤3.5 ps even with 100 mVPP VDD ripple at 10–500 kHz
Runt suppression	Hardware-level glitch suppression on OE and power-on prevents false clock edges during enable/disable transitions
Comprehensive production test	100% crystal ESR and DLD testing ensures long-term stability and mechanical robustness under thermal cycling and vibration

Applications

PCI Express Clocking	Gigabit Ethernet PHY Timing
Use Scenario: Reference clock source for PCIe Gen3 root complex and endpoint devices requiring dual-lane clocking schemes. IC Role / Device Role / Timing Role: Primary 100 MHz system clock and 156.25 MHz SerDes reference clock, selected dynamically via FS pin during link training. Use Value: Eliminates separate oscillators for system and SerDes domains, reducing BOM count and PCB area while maintaining <0.5 ps jitter margin.	Use Scenario: Synchronizing 1000BASE-X and SFP+ transceivers in enterprise switches with independent MAC/PHY clock domains. IC Role / Device Role / Timing Role: Dual-output LVPECL oscillator providing 156.25 MHz for 10G Ethernet lanes and 100 MHz for management interface timing. Use Value: Enables deterministic frequency switching during link renegotiation without external clock mux or reconfiguration delay.
FPGA Configuration Clock	Telecom Line Card Timing
Use Scenario: Boot-time and runtime clock source for Xilinx UltraScale+ and Intel Stratix 10 FPGAs requiring configurable startup and reconfiguration clocks. IC Role / Device Role / Timing Role: Supplies 100 MHz configuration clock and 156.25 MHz transceiver reference clock, both LVPECL-compatible. Use Value: Reduces FPGA I/O pin count by eliminating external clock multiplexers and simplifies layout with matched differential pair routing.	Use Scenario: Timing engine for multi-port TDM-over-IP line cards supporting SONET OC-48 and OTN OTU2 interfaces. IC Role / Device Role / Timing Role: Provides traceable 156.25 MHz sync clock for OTN framing and 100 MHz for control-plane processors. Use Value: Meets GR-1244-CORE jitter compliance (0.31 ps RMS) and supports holdover during network synchronization loss.

PCI Express Clocking

Gigabit Ethernet PHY Timing

Use Scenario: Reference clock source for PCIe Gen3 root complex and endpoint devices requiring dual-lane clocking schemes.

IC Role / Device Role / Timing Role: Primary 100 MHz system clock and 156.25 MHz SerDes reference clock, selected dynamically via FS pin during link training.

Use Value: Eliminates separate oscillators for system and SerDes domains, reducing BOM count and PCB area while maintaining <0.5 ps jitter margin.

Use Scenario: Synchronizing 1000BASE-X and SFP+ transceivers in enterprise switches with independent MAC/PHY clock domains.

IC Role / Device Role / Timing Role: Dual-output LVPECL oscillator providing 156.25 MHz for 10G Ethernet lanes and 100 MHz for management interface timing.

Use Value: Enables deterministic frequency switching during link renegotiation without external clock mux or reconfiguration delay.

FPGA Configuration Clock

Telecom Line Card Timing

Use Scenario: Boot-time and runtime clock source for Xilinx UltraScale+ and Intel Stratix 10 FPGAs requiring configurable startup and reconfiguration clocks.

IC Role / Device Role / Timing Role: Supplies 100 MHz configuration clock and 156.25 MHz transceiver reference clock, both LVPECL-compatible.

Use Value: Reduces FPGA I/O pin count by eliminating external clock multiplexers and simplifies layout with matched differential pair routing.

Use Scenario: Timing engine for multi-port TDM-over-IP line cards supporting SONET OC-48 and OTN OTU2 interfaces.

IC Role / Device Role / Timing Role: Provides traceable 156.25 MHz sync clock for OTN framing and 100 MHz for control-plane processors.

Use Value: Meets GR-1244-CORE jitter compliance (0.31 ps RMS) and supports holdover during network synchronization loss.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-frequency oscillator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si513BBA000594AAG	Same package and pinout, but ±50 ppm total stability (Grade B) and 2.5 V supply	Lower stability grade and reduced supply voltage limit suitability for cost-sensitive industrial controls over telecom-grade systems	Select only if 100/156.25 MHz frequencies, 2.5 V rail, and ±50 ppm stability meet system timing budget
Si512ACA000594AAG	Same frequencies/stability/supply, but OE on pin 2 and CMOS output (not LVPECL)	CMOS output lacks differential noise immunity; unsuitable for >150 MHz traces or noisy backplanes	Choose only for single-ended, lower-power, short-trace applications where LVPECL's drive strength and jitter are unnecessary

Compared with Si513BBA000594AAG, the 513ACA000594AAG provides tighter ±30 ppm stability and 3.3 V compatibility for legacy logic systems; versus Si512ACA000594AAG, it delivers LVPECL's superior jitter performance and noise rejection essential for high-speed serial links.

Availability

513ACA000594AAG is available at Aetrix Electronics and suitable for PCI Express Gen3/Gen4, Gigabit Ethernet PHY, FPGA transceiver, and telecom line card applications requiring stable component supply with guaranteed lead times under 4 weeks.

Supply support for 513ACA000594AAG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with broad manufacturing scale and automotive/industrial qualification.

The Si512/513 family was designed specifically for high-reliability dual-clock generation in networking, data center, and telecom equipment where programmability, low jitter, and long-term stability are critical.

FAQ

What are the factory-programmed frequencies of the 513ACA000594AAG?

The 513ACA000594AAG is factory-programmed with two precise output frequencies: 100.000000 MHz and 156.250000 MHz. These values are permanently stored in the device and selected in real time using the FS pin-low selects 100 MHz, high selects 156.25 MHz. Both frequencies are delivered simultaneously on the LVPECL differential outputs (CLK+/CLK–) when OE is asserted.

Does the 513ACA000594AAG support LVPECL output termination, and what is the recommended load?

Yes, the 513ACA000594AAG supports LVPECL output with a specified termination of 50 Ω to VDD – 2 V on both CLK+ and CLK– pins. This matches standard LVPECL receiver input impedance and ensures optimal signal integrity, common-mode voltage (VDD – 1.4 V), and swing (0.55–0.90 VPPSE). Incorrect termination causes degraded jitter and duty cycle distortion.

How does the internal LDO in the 513ACA000594AAG improve jitter performance?

The on-chip LDO regulator in the 513ACA000594AAG actively filters supply noise, limiting additive RMS jitter to ≤3.5 ps even with 100 mVPP sinusoidal noise injected at 10–500 kHz on VDD. This eliminates the need for external filtering components and maintains sub-0.5 ps phase jitter in electrically noisy environments such as switch fabric boards or power supply proximity zones.

What is the meaning of "Grade C" stability in the 513ACA000594AAG part number?

"Grade C" in the 513ACA000594AAG denotes ±30 ppm total frequency stability over the full operating range, including initial calibration error, temperature variation (–40 to +85 °C), supply voltage change, load variation, mechanical stress, and 10-year aging at 40 °C. This grade meets GR-1244-CORE and Telcordia SR-NEBS Level 3 requirements for telecom infrastructure timing.

Can the 513ACA000594AAG be used in place of a standard single-output XO?

Yes, the 513ACA000594AAG can replace a single-output XO by fixing the FS pin to a static logic level (e.g., tie to VDD for 156.25 MHz only) and using only one output phase if needed. However, its full value is realized in dual-clock architectures-using both frequencies dynamically avoids clock muxes, reduces latency, and simplifies timing closure in multi-domain SoCs and FPGAs.

513ACA000594AAG Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: Si513

Package/Case:: 6-SMD, No Lead

Packaging:: Strip

Product Status:: Active

Base Resonator:: Crystal

Type:: XO (Standard)

Frequency - Output 1:: 125MHz

Frequency - Output 2:: -

Frequency - Output 3:: -

Frequency - Output 4:: -

Function:: Enable/Disable

Output:: LVPECL

Voltage - Supply:: 3.3V

Frequency Stability:: ±20ppm

Operating Temperature:: -40°C ~ 85°C

Current - Supply (Max):: 43mA

Ratings:: -

Size / Dimension:: 0.276" L x 0.197" W (7.00mm x 5.00mm)

Height:: 0.071" (1.80mm)

Supplier Device Package:: -

513ACA000594AAG FAQ

1.How can I place an order for 513ACA000594AAG through Aetrix?

Please submit a Request for Quotation (RFQ) for 513ACA000594AAG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 513ACA000594AAG reliable?

The price and inventory of 513ACA000594AAG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 513ACA000594AAG is usually 5 days.

3.What payment methods are accepted for 513ACA000594AAG?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 513ACA000594AAG transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 513ACA000594AAG?

513ACA000594AAG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 513ACA000594AAG order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 513ACA000594AAG?

For technical support, including 513ACA000594AAG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 513ACA000594AAG requirements.

6.How does Aetrix verify that 513ACA000594AAG is sourced from the original manufacturer or authorized distributors?

All 513ACA000594AAG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 513ACA000594AAG meets industry standards.

7.What is the process for return or replacement of 513ACA000594AAG?

All 513ACA000594AAG units undergo pre-shipment inspection (PSI). If there is an issue with 513ACA000594AAG, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 513ACA000594AAG part is unused and in its original packaging.

Return procedure for 513ACA000594AAG:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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