Skyworks Solutions Inc. 513FCA000442BAGR

Overview

513FCA000442BAGR from Skyworks Solutions is a dual-frequency crystal oscillator (XO) with factory-programmed frequencies of 100 MHz and 125 MHz, ±30 ppm total stability (Grade C), 3.3 V supply, LVDS output format, and 3.2 × 5.0 mm 6-pin package. It delivers low-jitter clocking for high-speed serial interfaces and supports frequency selection via the FS pin.

For engineers reviewing the 513FCA000442BAGR datasheet, 513FCA000442BAGR pinout, 513FCA000442BAGR application, or 513FCA000442BAGR equivalent, this device serves as a programmable, dual-output timing source requiring precise jitter control, stable dual-frequency switching, and industrial-temperature operation in space-constrained designs.

Technical Context

The 513FCA000442BAGR implements Skyworks' DSPLL® synthesis architecture using a fixed crystal resonator and an on-chip PLL to generate two user-defined frequencies across 100 kHz–250 MHz. Its LVDS output pair (CLK+, CLK−) provides differential signaling with 48–52% duty cycle and sub-2.1 ps RMS period jitter at 125 MHz.

Frequency selection is controlled by the FS pin (active-high logic), while OE enables/disables outputs with runt suppression. An integrated LDO regulator filters supply noise, enabling robust operation in electrically noisy environments without external filtering components.

Key Specifications

Pinout & Package

Package: 3.2 × 5.0 mm, 6-pin surface-mount CLCC (RoHS-compliant, lead-free).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-frequency oscillator applications.

Compared with Si513FCA000104BAGR and Si512FCA000442BAGR, the 513FCA000442BAGR uniquely balances PCIe/Ethernet frequency alignment, LVDS noise immunity, and industrial thermal margin - making it optimal for high-density networking and compute platforms where jitter, layout density, and dual-domain timing coexist.

Availability

513FCA000442BAGR is available at Aetrix Electronics and suitable for PCIe Gen3/Gen4 reference clocking, Gigabit Ethernet PHY synchronization, and FPGA transceiver timing requiring stable component supply, consistent parametric performance, and long-lifecycle availability.

Supply support for 513FCA000442BAGR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog products.

The Si512/513 product line was designed to replace traditional fixed-frequency XOs with programmable, dual-output timing devices for high-speed digital systems requiring flexible, low-jitter clock generation in compact form factors.

FAQ

What are the factory-programmed frequencies of the 513FCA000442BAGR?

The 513FCA000442BAGR is factory-programmed for two precise output frequencies: 100 MHz and 125 MHz. These values are permanently stored during manufacturing and cannot be altered in-circuit. The FS pin selects between them - FS = 0 yields 100 MHz, FS = 1 yields 125 MHz - enabling dynamic clock domain switching without firmware intervention. Both frequencies are verified per Table 2 in the Si512/513 datasheet Rev. 1.2.

Does the 513FCA000442BAGR support LVDS output with proper termination?

Yes, the 513FCA000442BAGR supports LVDS output with a nominal common-mode voltage of 1.13–1.33 V (at 3.3 V supply) and requires 100 Ω differential termination across CLK+ and CLK−. This matches standard LVDS receiver inputs and ensures signal integrity, jitter performance, and EMI compliance. The device's LVDS drive strength and rise/fall times (≤800 ps) are characterized per Table 3 and Table 5 of the datasheet.

What is the total frequency stability specification for the 513FCA000442BAGR?

The 513FCA000442BAGR has a total frequency stability of ±30 ppm (Grade C), as defined in Table 2 of the Si512/513 datasheet. This value includes initial calibration error, temperature variation (–40 to +85 °C), supply voltage change (±10%), load variation, mechanical stress (shock/vibration), and 10-year aging at 40 °C - all guaranteed over the full operating range without derating.

How does the OE pin function on the 513FCA000442BAGR?

The OE (Output Enable) pin on the 513FCA000442BAGR is active-high and features an internal pull-up resistor (~45 kΩ). When OE = high (≥0.8 × VDD), both LVDS outputs are enabled; when OE = low (≤0.2 × VDD), outputs enter high-impedance tri-state with ≤18 mA supply current. Runt suppression prevents glitches during transitions, and the pin is located on Pin 1 per Table 14 (Si513 LVPECL/LVDS/HCSL/Dual CMOS pinout).

Is the 513FCA000442BAGR pin-compatible with other Si513 variants in the same package?

Yes, the 513FCA000442BAGR uses the standard Si513 6-pin 3.2 × 5.0 mm CLCC footprint with identical pin assignments: Pin 1 = OE, Pin 2 = FS, Pin 3 = GND, Pin 4 = CLK+, Pin 5 = CLK−, Pin 6 = VDD. All Si513 variants (regardless of frequency, stability grade, or output format) share this mechanical and electrical pinout, enabling direct replacement within the same package option (B = 3.2 × 5.0 mm).